cs89712 Cirrus Logic, Inc., cs89712 Datasheet - Page 81

• Manufacturer Part Number: cs89712
• Description: High-performance, Low-power System-on-chip With 10base-t Ethernet Controller
• Manufacturer: Cirrus Logic, Inc.

DS502PP2
11
12
13
14
15
16:17
18
19
Bit
DBGEN: Setting this bit will enable the debug mode. In this mode, all internal accesses are out-
put as if they were reads or writes to the expansion memory addressed by nCS5. nCS5 will still
be active in its standard address range. In addition, the internal interrupt request and fast inter-
rupt request signals to the ARM720T processor are output on Port E, bits 1 and 2. Note that
these bits must be programmed to be outputs before this functionality can be observed. The
clock to the CPU is output on Port E, Bit 0 to delineate individual accesses. For example, in
debug mode:
LCDEN: LCD enable bit. Setting this bit enables the LCD controller.
CDENTX: Codec interface enable TX bit. Setting this bit enables the codec interface for data
transmission to an external codec device.
CDENRX: Codec interface enable RX bit. Setting this bit enables the codec interface for data
reception from an external codec device.
Note: Both CDENRX and CDENTX need to be enabled / disabled in tandem, otherwise data may
SIREN: HP SIR protocol encoding enable bit. This bit will have no effect if the UART is not
enabled.
ADCKSEL: Microwire / SPI peripheral clock speed select. This two-bit field selects the frequency
of the ADC sample clock, which is twice the frequency of the synchronous serial ADC interface
clock. The table below shows the available frequencies for operation when in PLL mode. These
bits are also used to select the shift clock frequency for the SSI2 interface when set into master
mode.
EXCKEN: External expansion clock enable. If this bit is set, the EXPCLK is enabled continuously
as a free running clock with the same frequency and phase as the CPU clock, assuming that the
main oscillator is running. This bit should not be left set all the time for power consumption rea-
sons. If the system enters the Standby State, the EXPCLK will become undefined. If this bit is
clear, EXPCLK will be active during memory cycles to expansion slots that have external wait
state generation enabled only.
WAKEDIS: Setting this bit disables waking up (exiting) from the Standby State, from either the
WAKEUP input pin or a keypress after one of the following signals became active: nPWRFL,
BATOK, nEXTPWR.
Note: Even though a keypress will not wake the device, a keypress interrupt will still be generated,
ADCKSEL
be lost.
if the keyboard interrupt is not masked, and this can be used to wake the device.
nCS5 = nCS5 or internal I/O strobe
00
01
10
11
PE2 = nFIQ
PE0 = CLK
PE1 = nIRQ
ADC Sample Frequency
(kHz) — SMPCLK
Table 37. SYSCON1 (Continued)
128
256
32
8
Description
ADC Clock Frequency
(kHz) — ADCCLK
128
16
64
4
CS89712
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