ltc4266a Linear Technology Corporation, ltc4266a Datasheet - Page 13

• Manufacturer Part Number: ltc4266a
• Description: Quad Poe/poe+/ltpoe++ Pse Controller
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4266A/LTC4266C is held inactive with all ports
off and all internal registers reset to their power-up states.
When RESET is pulled high, the LTC4266A/LTC4266C
begins normal operation. RESET can be connected to
an external capacitor or RC network to provide a power
turn-on delay. Internal filtering of the RESET pin prevents
glitches less than 1μs wide from resetting the LTC4266A/
LTC4266C. Internally pulled up to V
MID: Midspan Mode Input. When high, the LTC4266A/
LTC4266C acts as a midspan device. Internally pulled
down to DGND.
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4266A/LTC4266C.
It will return to a high impedance state when bits 6 or 7
are set in the Reset PB register (1Ah). The INT signal can
be used to generate an interrupt to the host processor,
eliminating the need for continuous software polling.
Individual INT events can be disabled using the Int Mask
register (01h). See the LTC4266A/LTC4266C Software
Programming documentation for more information. The
INT pin is only updated between I
SCL: Serial Clock Input. High impedance clock input for the
I
SDAOUT: Serial Data Output, Open Drain Data Output for
the I
uses two pins to implement the bidirectional SDA function
to simplify optoisolation of the I
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAOUT should be grounded or left floating if
not used. See the Applications Information section for
more information.
SDAIN: Serial Data Input. High impedance data input for
the I
uses two pins to implement the bidirectional SDA function
to simplify optoisolation of the I
standard bidirectional SDA pin, tie SDAOUT and SDAIN
together. SDAIN must be tied high if not used. See the
Applications Information section for more information.
2
C serial interface bus. SCL must be tied high if not used.
2
2
C Serial Interface Bus. The LTC4266A/LTC4266C
C serial interface bus. The LTC4266A/LTC4266C
2
2
2
C bus. To implement a
C bus. To implement a
C transactions.
DD
.
AD3: Address Bit 3. Tie the address pins high or low to set
the I
responds. This address will be 010A
pulled up to V
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
DGND: Digital Ground. DGND is the return for the V
supply.
V
relative to DGND. V
the LTC4266A/LTC4266C with at least a 0.1μF capacitor.
SHDN1: Shutdown Port 1, Active Low. When pulled low,
SHDN1 shuts down port 1, regardless of the state of the
internal registers. Pulling SHDN1 low is equivalent to set-
ting the Reset Port 1 bit in the Reset Pushbutton register
(1Ah). Internal filtering of the SHDN1 pin prevents glitches
less than 1μs wide from resetting the port. Internally pulled
up to V
SHDN2: Shutdown Port 2, Active Low. See SHDN1.
SHDN3: Shutdown Port 3, Active Low. See SHDN1.
SHDN4: Shutdown Port 4, Active Low. See SHDN1.
AGND: Analog Ground. AGND is the return for the V
supply.
SENSE4: Port 4 Current Sense Input. SENSE4 monitors
the external MOSFET current via a 0.5Ω or 0.25Ω sense
resistor between SENSE4 and V
across the sense resistor exceeds the overcurrent detection
threshold V
the voltage across the sense resistor reaches the current
limit threshold V
maintain constant current in the external MOSFET. See
the Applications Information section for further details.
If the port is unused, the SENSE4 pin must be tied to V
DD
: Logic Power Supply. Connect to a 3.3V power supply
2
C serial address to which the LTC4266A/LTC4266C
DD
.
CUT
LTC4266A/LTC4266C
DD
, the current limit fault timer counts up. If
.
LIM
, the GATE4 pin voltage is lowered to
DD
must be bypassed to DGND near
EE
. Whenever the voltage
3
A
2
A
1
A
0
b. Internally
13
4266acfa
EE
DD
EE
.