ltc4266a Linear Technology Corporation, ltc4266a Datasheet - Page 24

• Manufacturer Part Number: ltc4266a
• Description: Quad Poe/poe+/ltpoe++ Pse Controller
• Manufacturer: Linear Technology Corporation

LTC4266A/LTC4266C
APPLICATIONS INFORMATION
they are staggered by at least 0.55μs to help reduce volt-
age transients on the main supply. If a port is turned off
via MSD, the corresponding Detection and Classification
Enable bits are cleared, so the port will remain off until
the host explicitly re-enables detection.
SERIAL DIGITAL INTERFACE
Overview
The LTC4266A/LTC4266C communicates with the host us-
ing a standard SMBus/I
LTC4266C is a slave-only device, and communicates with
the host master using the standard SMBus protocols.
Interrupts are signaled to the host via the INT pin. The
Timing Diagrams (Figures 5 through 9) show typical
communication waveforms and their timing relationships.
More information about the SMBus data protocols can be
found at www.smbus.org.
The LTC4266A/LTC4266C requires both the V
supply rails to be present for the serial interface to function.
Bus Addressing
The LTC4266A/LTC4266C’s primary serial bus address is
010xxxxb, with the lower four bits set by the AD3-AD0
pins; this allows up to 16 LTC4266A/LTC4266Cs on a
single bus. All LTC4266A/LTC4266Cs also respond to
the address 0110000b, allowing the host to write the
same command (typically configuration commands) to
multiple LTC4266A/LTC4266Cs in a single transaction. If
the LTC4266A/LTC4266C is asserting the INT pin, it will
also respond to the alert response address (0001100b)
per the SMBus spec.
Interrupts and SMBAlert
Most LTC4266A/LTC4266C port events can be configured
to trigger an interrupt, asserting the INT pin and alerting
the host to the event. This removes the need for the host
to poll the LTC4266A/LTC4266C, minimizing serial bus
traffic and conserving host CPU cycles. Multiple LTC4266A/
LTC4266Cs can share a common INT line, with the host
using the SMBAlert protocol (ARA) to determine which
LTC4266A/LTC4266C caused an interrupt.
24
2
C 2-wire interface. The LTC4266A/
DD
and V
EE
Register Description
For information on serial bus usage and device configura-
tion and status, refer to the LTC4266A/LTC4266C Software
Programming documentation.
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4266A/LTC4266C requires two supply voltages to
operate. V
V
for Type 1 PSEs, –51V to –57V for Type 2 PSEs or –54.75V
to –57V for LTPoE ++ PSEs, relative to AGND. The relation-
ship between the two grounds is not fixed; AGND can be
referenced to any level from V
should typically be tied to either V
V
LTC4266C circuitry, and draws a maximum of 3mA. A
ceramic decoupling cap of at least 0.1μF should be placed
from V
LTC4266C chip.
Figure 14 shows a three component low dropout regula-
tor for a negative supply to DGND generated from the
negative V
negative referenced to AGND. This regulator drives a single
LTC4266A/LTC4266C device. In Figure 15, DGND is tied
to AGND in this boost converter circuit for a positive V
supply of 3.3V above AGND. This circuit can drive multiple
LTC4266A/LTC4266C devices and opto couplers.
EE
DD
requires a negative voltage of between –45V and –57V
provides power for most of the internal LTC4266A/
DD
CMHZ4687-4.3V
to DGND, as close as practical to each LTC4266A/
DD
EE
AGND
V
requires 3.3V (nominally) relative to DGND.
supply. V
EE
Figure 14. Negative LDO to DGND
750k
D1
R5
DD
0.1μF
C1
is tied to AGND and DGND is
Q2
CMPTA92
DD
DD
V
DGND
to DGND, although it
DD
LTC4266
4266AC F14
or DGND.
AGND
V
EE
4266acfa
DD