ltc4266a Linear Technology Corporation, ltc4266a Datasheet - Page 6

• Manufacturer Part Number: ltc4266a
• Description: Quad Poe/poe+/ltpoe++ Pse Controller
• Manufacturer: Linear Technology Corporation

ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T
otherwise noted. (Notes 3, 4)
LTC4266A/LTC4266C
SYMBOL
I
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4266A/LTC4266C operates with a negative supply voltage
(with respect to ground). To avoid confusion, voltages in this data sheet
are referred to in terms of absolute magnitude.
Note 5: t
6
2
1
2
3
4
5
6
7
8
r
f
C Timing
DIS
is the same as t
PARAMETER
Clock Frequency
Bus Free Time
Start Hold Time
SCL Low Time
SCL High Time
Data Hold Time
Data Set-Up Time
Start Set-Up Time
Stop Set-Up Time
SCL, SDAIN Rise Time
SCL, SDAIN Fall Time
Fault Present to INT Pin Low
Stop Condition to INT Pin Low
ARA to INT Pin High Time
SCL Fall to ACK Low
MPDO
defined by IEEE 802.3at.
A
CONDITIONS
(Note 7)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9) Data into Chip
Data Out of Chip
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
Figure 5 (Notes 7, 9)
(Notes 7, 9, 10)
(Notes 7, 9, 10)
(Notes 7, 9)
(Notes 7, 9)
= 25°C. AGND – V
The
l
denotes the specifications which apply over the full operating
Note 6: The LTC4266A/LTC4266C digital interface operates with respect to
DGND. All logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
t
Note 9: Values measured at V
Note 10: If fault condition occurs during an I
will not be pulled down until a stop condition is present on the I
Note 11: Load Characteristic of the LTC4266A/LTC4266C during Mark:
Note 12: See the LTC4266A/LTC4266C Software Programming
documentation for information on serial bus usage and device
configuration and status registers.
MPS
EE
7V < (AGND – V
within any t
= 54V, AGND = DGND, and V
MPDO
OUTn
time window.
) < 10V or I
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
ILD(MAX)
MIN
480
240
480
240
240
240
OUT
60
80
DD
and V
< 50μA
– DGND = 3.3V unless
IHD(MIN)
2
C transaction, the INT pin
TYP
.
MAX
120
120
150
120
1.5
1.5
60
1
2
C bus.
4266acfa
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
ns