ltc4266a Linear Technology Corporation, ltc4266a Datasheet - Page 14

• Manufacturer Part Number: ltc4266a
• Description: Quad Poe/poe+/ltpoe++ Pse Controller
• Manufacturer: Linear Technology Corporation

LTC4266A/LTC4266C
PIN FUNCTIONS
GATE4: Port 4 Gate Drive. GATE4 should be connected
to the gate of the external MOSFET for port 4. When the
MOSFET is turned on, the gate voltage is driven to 12V
(typ) above V
voltage at GATE4 will be reduced to maintain constant
current through the external MOSFET. If the fault timer
expires, GATE4 is pulled down, turning the MOSFET off
and recording a t
float the GATE4 pin.
OUT4: Port 4 Output Voltage Monitor. OUT4 should be
connected to the output port. A current limit foldback
circuit limits the power dissipation in the external MOSFET
by reducing the current limit threshold when the drain-to-
source voltage exceeds 10V. The port 4 Power Good bit is
set when the voltage from OUT4 to V
(typ). A 500k resistor is connected internally from OUT4
to AGND when the port is idle. If the port is unused, OUT4
pin must be floated.
SENSE3: Port 3 Current Sense Input. See SENSE4.
GATE3: Port 3 Gate Drive. See GATE4.
OUT3: Port 3 Output Voltage Monitor. See OUT4.
V
supply, relative to AGND.
14
EE
: Main Supply Input. Connect to a –45V to –57V
EE
. During a current limit condition, the
CUT
or t
START
event. If the port is unused,
EE
drops below 2.4V
SENSE2: Port 2 Current Sense Input. See SENSE4.
GATE2: Port 2 Gate Drive. See GATE4.
OUT2: Port 2 Output Voltage Monitor. See OUT4.
SENSE1: Port 1 Current Sense Input. See SENSE4.
GATE1: Port 1 Gate Drive. See GATE 4.
OUT1: Port 1 Output Voltage Monitor. See OUT4.
AUTO: AUTO Pin Mode Input. AUTO pin mode allows the
LTC4266A/LTC4266C to detect and power up a PD even
if there is no host controller present on the I
voltage of the AUTO pin determines the state of the internal
registers when the LTC4266A/LTC4266C is reset or comes
out of V
Programming documentation). The states of these register
bits can subsequently be changed via the I
The real-time state of the AUTO pin is read at bit 0 in the
Pin Status register (11h). Internally pulled down to DGND.
Must be tied locally to either V
MSD: Maskable Shutdown Input. Active low. When pulled
low, all ports that have their corresponding mask bit set
in the Misc Config register (17h) will be reset, equivalent
to pulling the SHDN pin low. Internal filtering of the MSD
pin prevents glitches less than 1μs wide from resetting
ports. Internally pulled up to V
DD
UVLO (see the LTC4266A/LTC4266C Software
DD
DD
.
or DGND.
2
2
C interface.
C bus. The
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