mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 33

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mg82fel308

Manufacturer Part Number
mg82fel308
Description
A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
Manufacturer
Megawin Technology
Datasheet
11.2. Interrupt Register
IE: Interrupt Enable Register
SFR Address
SFR Page
Bit 7: EA, All interrupts enable register.
0: Global disables all interrupts.
1: Global enables all interrupts.
Bit 6: Reserved.
Bit 5: ET2, Timer 2 interrupt enable register.
0: Disable Timer 2 interrupt.
1: Enable Timer 2 interrupt.
Bit 4: ES, Serial port interrupt enable register.
0: Disable serial port interrupt.
1: Enable serial port interrupt.
Bit 3: ET1, Timer 1 interrupt enable register.
0: Disable Timer 1 interrupt.
1: Enable Timer 1 interrupt.
Bit 2: EX1, External interrupt 1 enable register.
0: Disable external interrupt 1.
1: Enable external interrupt 1.
Bit 1: ET0, Timer 0 interrupt enable register.
0: Disable Timer 0 interrupt.
1: Enable Timer 1 interrupt.
Bit 0: EX0, External interrupt 0 enable register.
0: Disable external interrupt 0.
1: Enable external interrupt 1.
XIFLG: External Interrupt Flag Register
SFR Address
SFR Page
Bit 7~4: Reserved.
Bit 3: IE5, External interrupt 5 Edge flag.
0: Cleared by hardware when the interrupt is starting to be serviced. It also could be cleared by CPU.
1: Set by hardware when external interrupt edge detected. It also could be set by CPU.
Bit 2: IE4, External interrupt 4 Edge flag.
0: Cleared by hardware when the interrupt is starting to be serviced. It also could be cleared by CPU.
1: Set by hardware when external interrupt edge detected. It also could be set by CPU.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
33/84
R/W
EA
--
7
7
R
MEGAWIN
MAKE YOU WIN
= 0xE8
= All
= 0xC0
= All
--
--
6
R
6
R
ET2
R/W
--
5
5
R
R/W
ES
--
4
4
R
Reset Value = 0X00-0000
Reset Value = XXXX-0000
ET1
R/W
IE5
R/W
3
3
EX1
R/W
R/W
IE4
2
2
MG82FE(L)308/316
ET0
R/W
R/W
IE3
1
1
Preliminary, v 0.04
EX0
R/W
IE2
R/W
0
0

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