mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 43

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

1: Set by software to specify falling edge triggered external interrupt 1.
Bit 1: IE0, Interrupt 0 Edge flag.
0: Cleared when interrupt processed on if transition-activated.
1: Set by hardware when external interrupt 0 edge is detected (transmitted or level-activated).
Bit 0: IT0: Interrupt 0 Type control bit.
0: Cleared by software to specify low level triggered external interrupt 0.
1: Set by software to specify falling edge triggered external interrupt 0.
TL0: Timer Low 0 Register
SFR Address
SFR Page
TH0: Timer High 0 Register
SFR Address
SFR Page
TL1: Timer Low 1 Register
SFR Address
SFR Page
TH1: Timer High 1 Register
SFR Address
SFR Page
AUXR2: Auxiliary Register 2
SFR Address
SFR Page
Bit 7: T0X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 6: T1X12, Timer 1 clock source selector while C/T=0.
0: Clear to select SYSCLK/12.
1: Set to select SYSCLK as the clock source.
Bit 1: T1CKOE, Timer 1 Clock Output Enable.
0: Disable Timer 1 clock output.
1: Enable Timer 1 clock output on P3.5.
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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TH0[7]
TH1[7]
T0X12
TL0[7]
TL1[7]
R/W
R/W
R/W
R/W
R/W
7
7
7
7
7
MEGAWIN
MAKE YOU WIN
TH0[6]
TH1[6]
T1X12
TL0[6]
TL1[6]
= 0x8A
= All
= 0x8C
= All
= 0x8B
= All
= 0x8D
= All
= 0x87
= All
R/W
R/W
R/W
R/W
R/W
6
6
6
6
6
URM0X6
TH0[5]
TH1[5]
TL0[5]
TL1[5]
R/W
R/W
R/W
R/W
R/W
5
5
5
5
5
TH0[4]
TH1[4]
TL0[4]
TL1[4]
R/W
R/W
R/W
R/W
--
4
4
4
4
4
R
Reset Value = 0000-0000
Reset Value = 0000-0000
Reset Value = 0000-0000
Reset Value = 0000-0000
Reset Value = 000X-XX00
TH0[3]
TH1[3]
TL0[3]
TL1[3]
R/W
R/W
R/W
R/W
--
3
3
3
3
3
R
TH0[2]
TH1[2]
TL0[2]
TL1[2]
R/W
R/W
R/W
R/W
--
2
2
2
2
2
R
T1CKOE
TH0[1]
TH1[1]
TL0[1]
TL1[1]
MG82FE(L)308/316
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
Preliminary, v 0.04
T0CKOE
TH0[0]
TH1[0]
TL0[0]
TL1[0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0