mg82fel308 Megawin Technology, mg82fel308 Datasheet - Page 59

• Manufacturer Part Number: mg82fel308
• Description: A Single-chip Microcontroller Based On A High Performance 1-t Architecture 80c51
• Manufacturer: Megawin Technology

13.3. Serial Port Mode 2 and Mode 3
11 bits are transmitted through TXD, or received through RXD: a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of 0
or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to select one of 1/16,
1/32 or 1/64 the system clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer
1 or Timer 2.
Figure 13-2 shows the data frame in Mode 2 and Mode 3. Figure 13-6 shows a functional diagram of the serial
port in Mode 2 and Mode 3. The receive portion is exactly the same as in Mode 1. The transmit portion differs
from Mode 1 only in the 9th bit of the transmit shift register.
The “write to SBUF” signal requests the Serial Port Controller to load TB8 into the 9th bit position of the transmit
shit register and starts the transmission. After receiving a transmission request, the UART engine would start the
transmission at the raising edge of TX Clock. The data in the SBUF would be serial output on the TXD pin with
the data frame as shown in Figure 13-2 and data width depend on TX Clock. After the end of 9th data
transmission, TI would be asserted by hardware to indicate the end of data transmission.
Reception is initiated when the UART engine detected 1-to-0 transition at RXD sampled by RCK. The data on the
RXD pin would be sampled by Bit Detector in UART engine. After the end of 9th data bit reception, RI would be
asserted by hardware to indicate the end of data reception and load the 9th data bit into RB8 in SCON register.
In all four modes, transmission is initiated by any instruction that use SBUF as a destination register. Reception is
initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming
start bit with 1-to-0 transition if REN=1.
13.4. Frame Error Detection
When used for framing error detection, the UART looks for missing stop bits in the communication. A missing
stop bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of
SCON.7 is determined by SMOD0 bit (PCON.6). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When SCON.7 functions as FE, it can only be cleared by firmware.
Refer to Figure 13-7.
Figure 13-7 UART Frame Error Detection
This document information is the intellectual property of Megawin Technology.
© Megawin Technology Co., Ltd. 2009 All rights reserved.
QP-7300-03D
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SCON
Start
MEGAWIN
MAKE YOU WIN
SM0/FE
D0
SM1
D1
SM2
D2
REN
PCON.SMOD0
D3
TB8
9-bit data
D4
SET FE bit if STOP=0
SM0 to UART mode control
RB8
D5
TI
RI
D6
D7
D8
Stop
MG82FE(L)308/316
Preliminary, v 0.04