fs6370 AMI Semiconductor, Inc., fs6370 Datasheet - Page 19

• Manufacturer Part Number: fs6370
• Description: Fs6370-01g Eeprom Programmable 3-pll Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

www.amis.com.
F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 / / F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 g g E E E E P P R R O O M M P P r r o o g g r r a a m m m m a a b b l l e e 3 3 - - P P L L L L C C l l o o c c k k G G e e n n e e r r a a t t o o r r I I C C
A A M M I I S S e e m m i i c c o o n n d d u u c c t t o o r r - - R R e e v v . . 2 2 . . 0 0 , , M M a a r r . . 0 0 5 5
P P a a r r a a m m e e t t e e r r
O O v v e e r r a a l l l l
EEPROM Write Cycle Time
Output Frequency*
VCO Frequency*
VCO Gain*
Loop Filter Time Constant*
Rise Time*
Fall Time*
Tristate Enable Delay*
Tristate Disable Delay*
Clock Stabilization Time*
D D i i v v i i d d e e r r M M o o d d u u l l u u s s
Feedback Divider
Reference Divider
Post Divider
C C l l o o c c k k O O u u t t p p u u t t s s ( ( P P L L L L A A c c l l o o c c k k v v i i a a C C L L K K _ _ A A p p i i n n ) )
Duty Cycle*
Jitter, Long Term (s
Jitter, Period (peak-peak)*
C C l l o o c c k k O O u u t t p p u u t t s s ( ( P P L L L L B B c c l l o o c c k k v v i i a a C C L L K K _ _ B B p p i i n n ) )
Duty Cycle*
Jitter, Long Term (s
Jitter, Period (peak-peak)*
C C l l o o c c k k O O u u t t p p u u t t s s ( ( P P L L L L _ _ C C c c l l o o c c k k v v i i a a C C L L K K _ _ C C p p i i n n ) )
Duty Cycle*
Jitter, Long Term (s
Jitter, Period (peak-peak)*
C C l l o o c c k k O O u u t t p p u u t t s s ( ( C C r r y y s s t t a a l l O O s s c c i i l l l l a a t t o o r r v v i i a a C C L L K K _ _ D D p p i i n n ) )
Duty Cycle*
Jitter, Long Term (s
Jitter, Period (peak-peak)*
Table 13: AC Timing Specifications
Unless otherwise stated, V
currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical.
y
y
y
y
(t))*
(t))*
(t))*
(t))*
DD
= 5.0V ± 10%, no load on any output, and ambient temperature range T
S S y y m m b b o o l l C C o o n n d d i i t t i i o o n n s s / / D D e e s s c c r r i i p p t t i i o o n n
t
f
f
A
t
t
t
t
t
N
N
N
t
t
T
T
T
T
T
T
wc
O
VCO
r
f
PZL,
PZL,
STB
j(LT)
j(DP)
j(LT)
J(DP)
j(LT)
J(DP)
j(LT)
J(DP)
VCO
F
R
P
t
t
PZH
PZH
V
V
V
V
LFTC bit = 0
LFTC bit = 1
V
V
V
V
Output active from power-up, RUN mode via PD pin
After last register is written, register program mode
See also Table 2
See also Table 8
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period
On rising edges 500ms apart at 2.5V relative to an ideal clock, C
N
On rising edges 500ms apart at 2.5V relative to an ideal clock, C
N
From rising edge to the next rising edge at 2.5V, C
other PLLs active
From rising edge to the next rising edge at 2.5V, C
other PLLs active (B=60MHz, C=40MHz, D=14.318MHz)
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period
On rising edges 500ms apart at 2.5V relative to an ideal clock, C
N
On rising edges 500ms apart at 2.5V relative to an ideal clock, C
N
From rising edge to the next rising edge at 2.5V, C
other PLLs active
From rising edge to the next rising edge at 2.5V, C
other PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period
On rising edges 500ms apart at 2.5V relative to an ideal clock, C
N
On rising edges 500ms apart at 2.5V relative to an ideal clock, C
N
From rising edge to the next rising edge at 2.5V, C
other PLLs active
From rising edge to the next rising edge at 2.5V, C
other PLLs active (A=50MHz, B=60MHz, D=14.318MHz)
Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period
On rising edges 500ms apart at 2.5V relative to an ideal clock, C
N
From rising edge to the next rising edge at 2.5V, C
(A=50MHz, B=60MHz, C=40MHz)
From rising edge to the next rising edge at 2.5V, C
From rising edge to the next rising edge at 2.5V, C
(A=50MHz, B=60MHz, C=40MHz)
R
PX
R
R
R
R
R
DD
DD
DD
DD
O
O
O
O
=63, N
=63, N
=63, N
=63, N
=63, N
=63, N
=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz)
= 0.5V to 4.5V; C
= 0.3V to 3.0V; C
= 4.5V to 0.5V; C
= 3.0V to 0.3V; C
= 5.5V
= 3.6V
= 5.5V
= 3.6V
PX
Px
Px
Px
Px
Px
=50, no other PLLs active
=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz)
=50, no other PLLs active
=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz)
=50, no other PLLs active
=50, no other PLLs active
L
L
L
L
= 15pF
= 15pF
= 15pF
= 15pF
A
19
= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not
L
L
L
L
L
L
L
L
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
L
=15pF, f
XIN
XIN
XIN
XIN
XIN
XIN
XIN
XIN
XIN
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, no other PLLs active
=14.318MHz, all other PLLs active
=14.318MHz, all other PLLs active
L
L
L
L
L
L
L
=15pF, f
=15pF, =14.318MHz, N
=15pF, f
=15pF, f
=15pF, f
=15pF, f
=15pF, f
XIN
XIN
XIN
XIN
XIN
XIN
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
=14.318MHz, N
F
F
F
F
F
F
=220, N
=220, N
=220, N
=220, N
=220, N
=220, N
R
R
R
R
R
R
=63, N
=63, N
=63, N
=63, N
=63, N
=63, N
F
=220, N
F
F
F
F
F
F
=220,
=220,
=220,
=220,
=220,
=220,
PX
PX
Px
Px
Px
Px
=50, no
=50, all
=50, no
=50, all
=50, no
=50, all
R
=63,
C C l l o o c c k k ( ( M M H H z z ) )
14.318
14.318
14.318
14.318
14.318
100
100
100
100
100
100
100
100
100
50
50
60
60
40
40
M M i i n n . .
0.8
0.8
40
40
45
45
45
45
1
1
8
1
1
T T y y p p . .
400
100
165
110
390
120
400
105
120
440
450
2.0
2.1
1.8
1.9
20
45
45
75
45
20
40
90
7
Data Sheet
M M a a x x . .
2047
150
100
230
170
255
50
55
55
55
55
4
8
8
1
MHz/V
U U n n i i t t s s
MHz
MHz
ms
ms
ms
ns
ns
ns
ns
ms
ps
ps
ps
ps
ps
ps
ps
ps
%
%
%
%