fs6370 AMI Semiconductor, Inc., fs6370 Datasheet - Page 5

• Manufacturer Part Number: fs6370
• Description: Fs6370-01g Eeprom Programmable 3-pll Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

www.amis.com.
F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 / / F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 g g E E E E P P R R O O M M P P r r o o g g r r a a m m m m a a b b l l e e 3 3 - - P P L L L L C C l l o o c c k k G G e e n n e e r r a a t t o o r r I I C C
A A M M I I S S e e m m i i c c o o n n d d u u c c t t o o r r - - R R e e v v . . 2 2 . . 0 0 , , M M a a r r . . 0 0 5 5
3 3 . . 2 2 P P o o s s t t D D i i v v i i d d e e r r M M u u x x e e s s
As shown in Figure 2, a mux in front of each post divider stage can select from any one of the three PLL frequencies or the reference frequency. The mux
selection is controlled by bits in the EEPROM or the control registers.
The input frequency on two of the four multiplexers (muxes C and D in Figure 2) can be altered without reprogramming by a logic-level input on the
SEL_CD pin.
3 3 . . 3 3 P P o o s s t t D D i i v v i i d d e e r r s s
A post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output
clock speeds that the device is required to generate. Second, it changes the basic PLL equation to:
where NP is the post divider modulus. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications
where frequencies must be achieved exactly.
The modulus on two of the four post dividers (post dividers C and D in Figure 2) can be altered without reprogramming by a logic level on the SEL_CD
pin.
4.0 Device Operation
The FS6370 has two modes of operation:
• P P r r o o g g r r a a m m m m o o d d e e : : during which either the EEPROM or the FS6370 control registers can be programmed directly with the desired PLL settings
• R R u u n n m m o o d d e e : : where the PLL settings stored the EEPROM are transferred to the FS6370 control registers on power-up, and the device then operates based
Note that the EEPROM locations are not physically the same registers used to control the FS6370.
Direct access to either the EEPROM or the FS6370 control registers is achieved in program mode. The EEPROM register contents are automatically
transferred to the FS6370 control registers in normal device operation (run mode).
4 4 . . 1 1 M M O O D D E E P P i i n n
The MODE pin controls the mode of operation. A logic-low places the FS6370 in program mode. A logic-high puts the device in run mode. A pull-up on
this pin defaults the device into run mode.
Reprogramming of either the control registers or the EEPROM is permitted at any time if the MODE pin is a logic-low.
Note, however, that a logic-high state on the MODE pin is latched so that only one transfer of EEPROM data to the FS6370 control registers can occur.
If a second transfer of EEPROM data into the FS6370 is desired, power (VDD) must be removed and reapplied to the device.
The MODE pin also controls the function of the PD/SCL and OE/SDA pins. In run mode, these two pins function as power-down (PD) and output enable
(OE) controls. In program mode, the pins function as the I
4 4 . . 2 2 S S E E L L _ _ C C D D P P i i n n
The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D, and post dividers C and D without having to reprogram the device. A
logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the SEL_CD pin selects the control bits with
"C2" or "D2" notation, per Table 3.
Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-divider(s) is/are
altered.
on those settings
2
C interface for clock (SCL) and data (SDA).
f
CLK
=
5
f
REF
æ
ç ç
è
N
N
F
R
ö
÷ ÷
ø
æ
ç ç
è
N
1
P
ö
÷ ÷
ø
Data Sheet