fs6370 AMI Semiconductor, Inc., fs6370 Datasheet - Page 9

• Manufacturer Part Number: fs6370
• Description: Fs6370-01g Eeprom Programmable 3-pll Clock Generator Ic
• Manufacturer: AMI Semiconductor, Inc.

www.amis.com.
F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 / / F F S S 6 6 3 3 7 7 0 0 - - 0 0 1 1 g g E E E E P P R R O O M M P P r r o o g g r r a a m m m m a a b b l l e e 3 3 - - P P L L L L C C l l o o c c k k G G e e n n e e r r a a t t o o r r I I C C
A A M M I I S S e e m m i i c c o o n n d d u u c c t t o o r r - - R R e e v v . . 2 2 . . 0 0 , , M M a a r r . . 0 0 5 5
8.1.4 Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs.
The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and
STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first 16 bytes
will overflow into the first register, then the second, and so on, in a first-in, first-overwritten fashion.
8.1.5 Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock
pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock
pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave.
In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
8 8 . . 2 2 I I
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The device accepts the following
I
8.2.1 Device Address
After generating a START condition, the bus master broadcasts a seven-bit device address followed by a R/W bit.
The device address of the FS6370 is:
Any one of eight possible addresses are available for the EEPROM. The least significant three bits are don't care's.
8.2.2 Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-
bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its
device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight
bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
8.2.3 Random Register Read Procedure
Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-
bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave
device acknowledges its device address. The register address is then written into the slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not
until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but
does generate a STOP condition.
2
C-bus commands.
A A 6 6
A A 6 6
1
1
2 2
C C - - b b u u s s O O p p e e r r a a t t i i o o n n
A A 5 5
A A 5 5
0
0
A A 4 4
A A 4 4
1
1
A A 3 3
A A 3 3
1
0
A A 2 2
A A 2 2
1
X
A A 1 1
A A 1 1
0
X
9
A A 0 0
A A 0 0
0
X
Data Sheet