pcf8813 NXP Semiconductors, pcf8813 Datasheet - Page 15

• Manufacturer Part Number: pcf8813
• Description: 67 + 1 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.13
This mode swaps the order of the order of the rows; see
Figs 13 and 14. The mode is useful to aide routing to
displays when it is not possible to pass tracks under the
device, as in the case of Tape Carrier Packages (TCP).
7.14
The order in which the rows are activated is a function of
bits Bottom Row Swap (BRS), Mirror Y (MY) and Normal
Partial mode (N/P). This has important implications when
the device is used either in COG or TCP applications.
When MY is set to 0, the RAM is accessed in a linear
manner, starting at R0, counting to R66, then jumping to
2004 Mar 05
handbook, full pagewidth
(67 + 1)
Bottom row swap
Output row order
102 pixels matrix LCD driver
Fig.13 Row order and interconnection with BRS = 0, MY = 0 and N/P = 1.
R0
R15
R16
R31
COLUMNS
INTERFACE
RAM
15
the end for the icon data. When MY is set to 1, the RAM is
still accessed in a linear manner but starting from the last
row, counting down to zero and then jumping to the icon
data.
When N/P is set to 1, the Free Programmable Mux Rate
(FPMR) mode is disabled and row addressing is in normal
mode (see Section 11.9), therefore counting is the same
as for MY = 0 and BRS = 0. When N/P is 0, FPMR mode
is enabled. Only 65 rows are addressed/read in FPMR
mode.
Figures 13 and 14 show the possibility of connecting the
icon row (row R67) at the top or bottom of the display.
MGW793
R67
R32
R47
R48
R63
R66
R67
Product specification
PCF8813