pcf8813 NXP Semiconductors, pcf8813 Datasheet - Page 24

• Manufacturer Part Number: pcf8813
• Description: 67 + 1 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
10.1.3
Both data and clock lines remain HIGH when the bus is not
busy (see Fig.27). A HIGH-to-LOW transition of the data
10.1.4
Each byte of eight bits is followed by an acknowledge bit
(see Fig.28). The acknowledge bit is a HIGH signal put on
the bus by the transmitter during which time the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
2004 Mar 05
handbook, full pagewidth
handbook, full pagewidth
(67 + 1)
S
A
TART AND STOP CONDITIONS
CKNOWLEDGE
BY TRANSMITTER
SDA
SCL
102 pixels matrix LCD driver
DATA OUTPUT
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
START condition
S
condition
START
Fig.27 Definition of start and stop conditions.
S
Fig.28 Acknowledge on the I
1
24
line, while the clock is HIGH is defined as the START
condition (S). A LOW-to-HIGH transition of the data line
while the clock is HIGH is defined as the STOP
condition (P).
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
2
2
C-bus.
not acknowledge
STOP condition
acknowledge
8
P
acknowledgement
clock pulse for
MBC622
9
MBC602
SDA
SCL
Product specification
PCF8813