pca8576c NXP Semiconductors, pca8576c Datasheet - Page 18

• Manufacturer Part Number: pca8576c
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCA8576C
Product data sheet
7.12 Data pointer
7.13 Sub-address counter
The following applies to
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see
stored starting at the display RAM address indicated by the data pointer (see
Once each byte is stored, the data pointer is automatically incremented based on the
selected LCD configuration.
The contents of the data pointer are incremented as follows:
If an I
Consequently, the data pointer must be rewritten prior to further RAM accesses.
The storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the device-select command (see
counter and the hardware subaddress do not match then data storage is blocked but the
data pointer will be incremented as if data storage had taken place. The subaddress
counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCA8576C occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
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In the static drive mode, the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1, and 2 to
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into
row 0, 1, 2, and 3 of two successive 4-bit RAM words.
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
2
C-bus data access terminates early, the state of the data pointer is unknown.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2010
Figure
11:
Universal LCD driver for low multiplex rates
Table
11). If the contents of the subaddress
Table
10). After this, the data byte is
PCA8576C
© NXP B.V. 2010. All rights reserved.
Figure
18 of 44
11).