pca8576d NXP Semiconductors, pca8576d Datasheet - Page 32

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pca8576d

Manufacturer Part Number
pca8576d
Description
Automotive 40 X 4 Lcd Segment Driver For Low Multiplex Rates Up To 1 4
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
PCA8576D
Product data sheet
12.2 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in
well).
Table 20.
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in
Display RAM
bits (rows)/
backplane
outputs (BPn)
0
1
2
3
Fig 22. Synchronization of the cascade for the various PCA8576D drive modes
Standard RAM filling in 1:3 multiplex drive mode
All information provided in this document is subject to legal disclaimers.
(1/2 bias)
(1/3 bias)
(1/3 bias)
(1/3 bias)
BP0
SYNC
SYNC
SYNC
SYNC
Display RAM addresses (columns)/segment outputs (Sn)
0
a7
a6
a5
-
BP0
BP0
BP0
BP0
Automotive 40 x 4 LCD segment driver for low multiplex rates
1
a4
a3
a2
-
Rev. 1 — 4 April 2011
2
a1
a0
-
-
(b) 1:2 multiplex drive mode.
(c) 1:3 multiplex drive mode.
(d) 1:4 multiplex drive mode.
3
b7
b6
b5
-
(a) static drive mode.
T
fr
4
b4
b3
b2
-
=
f
1
fr
5
b1
b0
-
-
c5
6
c7
c6
-
Table
Table 20
7
c4
c3
c2
-
21.
PCA8576D
mgl755
(see
8
c1
c0
-
-
© NXP B.V. 2011. All rights reserved.
Figure 11
9
d7
d6
d5
-
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