stlc3075 STMicroelectronics, stlc3075 Datasheet - Page 30

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stlc3075

Manufacturer Part Number
stlc3075
Description
Integrated Pots Interface For Home Access Gateway And Wll
Manufacturer
STMicroelectronics
Datasheet
Measurement configurations
Appendix A
A.1
30/36
STLC3075 test circuits
Referring to the application diagram as shown on
channel
configuration
configuration for each measurement.
All measurements requiring DC current termination should be performed using ’Wandel &
Glittering’ DC Loop Holding Circuit GH-1’ or equivalent.
Figure 13. 2W return loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
Figure 14. THL trans hybrid loss THL = 20Log|Vrx/Vtx /
E
and using the typical values from
Measurement configurations
and
1Kohm
1Kohm
600ohm
Table 11: External components @gain set = 0
600ohm
Zref
200 to 6kHz
Zin = 100K
DC mac
100mA
100µF
100µF
W&G GH1
Vs
200 to 6kHz
Zin = 100K
DC mac
100mA
100µF
100µF
W&G GH1
Table 6: External components for buckboost
RING
TIP
Figure 10: Application diagram with P-
application circuit
STLC3075
find below the proper
RING
TIP
TX
RX
application circuit
STLC3075
Vrx
Vtx
STLC3075
TX
RX

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