stlc3075 STMicroelectronics, stlc3075 Datasheet - Page 5

• Manufacturer Part Number: stlc3075
• Description: Integrated Pots Interface For Home Access Gateway And Wll
• Manufacturer: STMicroelectronics

STLC3075
Table 1.
39, 40, 42
6, 22, 38,
N°
10
11
12
13
14
15
16
17
18
19
20
21
23
1
2
3
4
5
7
8
9
D0
D1
D2
PD
Gain SET
NC
DET
CKTTX
CTTX1
CTTX2
RTTX
FTTX
RX
ZAC1
ZAC
RS
ZB
CAC
TX
CZ
VF
CLK
Pin description
Pin
Control interface: input bit 0
Control interface: input bit 1
Control interface: input bit 2
Power down input. Normally connected to CVCC (or to logic level high)
Control gain interface:
0 Level R
1 Level R
Not connected
Logic interface output of the supervision detector (active low)
Metering pulse clock input (12 kHz or 16kHz square wave)
Metering burst shaping external capacitor
Metering burst shaping external capacitor
Metering pulse cancellation buffer output. TTX filter network should be
connected to this point.
If not used, should be left open.
Metering pulse buffer input this signal is sent to the line and used to
perform TTX filtering
4 wires input port (RX input). A 100k external resistor must be connected
to AGND via the bias input stage. This signal refers to AGND. If connected
to single supply CODEC output it must be DC decoupled with proper
capacitor.
RX buffer output (the AC impedance is connected from this node to ZAC)
AC impedance synthesis
Protection resistors image
(the image resistor is connected from this node to ZAC)
Balance network for 2 to 4 wire conversion (the balance impedance ZB is
connected from this node to AGND. ZA impedance is connected from this
node to ZAC1).
AC feedback input, AC/DC split capacitor (CAC)
4 wire output port (TX output). The signal is referred to AGND. If connected
to single supply CODEC input it must be DC decoupled with proper
capacitor.
Flyback compensation
Feedback input for DC/DC converter controller
Power switch controller clock (typ. 125KHz). This pin can also be
connected to CVCC or AGND. When the CLK pin is connected to CVCC an
internal auto-oscillation is internally generated and it is used instead of the
external clock. When the CLK pin is connected to AGND, the GATE output
is disabled.
xgain
xgain
= 0dB T
= +6dB T
xgain
xgain
= -12dB
= -12dB
Function
Pin description
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