adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet - Page 10

• Manufacturer Part Number: adc12ds105cisq
• Description: Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
• Manufacturer: National Semiconductor Corporation

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LVDS DC CHARACTERISTICS
V
delta
V
V
delta V
IOS
LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS
t
t
t
t
t
t
t
t
t
t
Symbol
DP
HO
SUO
FP
FDC
DFS
R
ODOR
DLD
SD
OD
OD
OS
, t
ADC12DS080 LVDS Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V
f
amplitude. Boldface limits apply for T
CLK
F
= 80 MHz, V
OS
Output Differential Voltage
(SDO+) - (SDO-)
Output Differential Voltage Unbalance
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
Output Data Bit Period
Output Data Edge to Output Clock Edge
Hold Time(Note 13)
Output Data Edge to Output Clock Edge
Set-Up Time(Note 13)
Frame Period
Frame Clock Duty Cycle(Note 13)
Data Edge to Frame Edge Skew
LVDS Rise/Fall Time
Output Delay of OR output
Serializer DLL Lock Time
Serializer Delay
CM
= V
Parameter
CMO
, C
L
= 5 pF/pin. Typical values are for T
MIN
≤
T
A
≤
R
R
R
R
DO = 0V, V
Single-Lane Mode
Dual-Lane Mode
Single-Lane Mode
Dual-Lane Mode
Single-Lane Mode
Dual-Lane Mode
Single-Lane Mode
Dual-Lane Mode
50% to 50%
C
From rising edge of CLKL to ORA/ORB
valid
R
T
L
L
L
L
L
L
MAX
=5pF to GND, R
=100Ω
= 100Ω
= 100Ω
= 100Ω
= 100Ω
. All other limits apply for T
IN
10
= 1.1V,
Conditions
A
= 25°C. Timing measurements are taken at 50% of the signal
OUT
=100Ω
A
= 25°C (Notes 8, 9)
A
= V
DR
(Note 10)
Typical
1.25
1.04
2.08
12.5
TBD
TBD
TBD
TBD
= +3.0V, Internal V
350
320
840
320
840
-10
25
50
4
Limits
1.125
1.375
250
450
±25
±25
45
55
REF
mV (max)
mV (max)
mV (max)
mA (max)
= +1.2V,
mV (min)
ps (max)
ps (max)
% (max)
(Limits)
V (max)
% (min)
V (min)
Units
ns
ps
ps
ns
ns
µs
ns