adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet - Page 12

• Manufacturer Part Number: adc12ds105cisq
• Description: Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
• Manufacturer: National Semiconductor Corporation

www.national.com
H3
SINAD
DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B,SCSb,SPI_EN,SCLK,SDI,TEST,WAM,DLC)
V
V
I
I
C
DIGITAL OUTPUT CHARACTERISTICS (ORA,ORB,SDO)
V
V
+I
−I
C
POWER SUPPLY CHARACTERISTICS
I
I
t
t
t
Symbol
Symbol
IN(1)
IN(0)
A
DR
CONV
AD
AJ
IN(1)
IN(0)
OUT(1)
OUT(0)
Symb
IN
OUT
SC
SC
ADC12DS105 Logic and Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V
f
other limits apply for T
ADC12DS105 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V
f
amplitude. Boldface limits apply for T
CLK
CLK
= 105 MHz, V
= 105 MHz, V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Digital Input Capacitance
Logical “1” Output Voltage
Logical “0” Output Voltage
Output Short Circuit Source Current
Output Short Circuit Sink Current
Digital Output Capacitance
Analog Supply Current
Digital Output Supply Current
Power Consumption
Power Down Power Consumption
Third Harmonic Distortion
Signal-to-Noise and Distortion Ratio
Maximum Clock Frequency
Minimum Clock Frequency
Conversion Latency
Aperture Delay
Aperture Jitter
CM
CM
= V
= V
A
Parameter
Parameter
Parameter
= 25°C (Notes 8, 9)
CMO
CMO
, C
, C
L
L
= 5 pF/pin. Typical values are for T
= 5 pF/pin. Typical values are for T
MIN
≤
T
A
≤
V
V
V
V
I
I
V
V
Full Operation
Full Operation
Clock disabled
OUT
OUT
In Single-Lane Mode
In Dual-Lane Mode
In Single-Lane Mode
In Dual-Lane Mode
Single-Lane Mode
Dual-Lane, Offset Mode
Dual-Lane, Word Aligned Mode
D
D
IN
IN
OUT
OUT
T
MAX
= 3.6V
= 3.0V
= 3.3V
= 0V
= −0.5 mA , V
= 1.6 mA, V
= 0V
= V
. All other limits apply for T
DR
12
f
f
f
f
IN
f
f
IN
Conditions
Conditions
IN
IN
IN
IN
Conditions
DR
= 240 MHz
= 240 MHz
A
= 10 MHz
= 70 MHz
= 10 MHz
= 70 MHz
DR
A
= 25°C. Timing measurements are taken at 50% of the signal
= 1.8V
= 25°C. Boldface limits apply for T
= 1.8V
A
= 25°C (Notes 8, 9)
A
A
= V
= V
(Note 10)
DR
DR
Typical
(Note 10)
(Note 10)
Typical
Typical
66.8
−88
−85
−83
70
69
= +3.3V, Internal V
= +3.3V, Internal V
1060
0.6
0.1
−10
−10
250
10
10
71
33
5
5
Limits
MIN
Limits
Limits
52.5
105
7.5
65
25
2.0
0.8
1.2
0.4
8
9
≤
T
A
REF
REF
≤
Clock Cycles
T
(Limits)
(Note 2)
MHz (max)
MHz (min)
mW (max)
= +1.2V,
mA (max)
= +1.2V,
Units
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
MAX
(Limits)
(Limits)
V (max)
V (max)
V (min)
V (min)
ps rms
Units
Units
mW
mA
mA
mA
µA
µA
pF
pF
ns
. All