adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet - Page 3

• Manufacturer Part Number: adc12ds105cisq
• Description: Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
• Manufacturer: National Semiconductor Corporation

ANALOG I/O
DIGITAL I/O
Pin Descriptions and Equivalent Circuits
Pin No.
13
14
11
10
59
29
18
28
19
3
2
5
7
9
6
LVDS_Bias
Reset_DLL
OF/DCS
Symbol
V
V
V
V
V
V
V
V
V
V
V
CLK
CMO
CMO
IN
IN
IN
IN
RP
RP
RN
RN
REF
A+
B+
A-
B-
A
B
A
B
A
B
Equivalent Circuit
3
Differential analog input pins. The differential full-scale input signal
level is 2V
mode voltage, V
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. An 0201 size 0.1 µF
capacitor should be placed between V
pins as possible, and a 1 µF capacitor should be placed in parallel.
V
for use as a temperature stable 1.5V reference.
It is recommended to use V
voltage, V
Reference Voltage. This device provides an internally developed
1.2V reference. When using the internal reference, V
decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series
inductance (ESL) capacitor.
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current.
LVDS Driver Bias Resistor is applied from this pin to Analog
Ground. The nominal value is 3.6KΩ
The clock input pin.
The analog inputs are sampled on the rising edge of the clock input.
Reset_DLL input. This pin is normally low. If the input clock
frequency is changed abruptly, the internal timing circuits may
become unlocked. Cycle this pin high for 1 microsecond to re-lock
the DLL. The DLL will lock in several microseconds after
Reset_DLL is asserted.
This is a four-state pin controlling the input clock mode and output
data format.
OF/DCS = V
cycle stabilization applied to the input clock
OF/DCS = AGND, output data format is offset binary, without duty
cycle stabilization applied to the input clock.
OF/DCS = (2/3)*V
stabilization applied to the input clock
OF/DCS = (1/3)*V
stabilization applied to the input clock.
Note: This signal has no effect when SPI_EN is high and the SPI
interface is enabled.
RP
and V
CM
P-P
RN
, for the differential analog inputs.
A
should not be loaded. V
with each input pin signal centered on a common
, output data format is 2's complement without duty
CM
A
A
.
, output data is 2's complement with duty cycle
, output data is offset binary with duty cycle
Description
CMO
to provide the common mode
CMO
RP
and V
may be loaded to 1mA
RN
as close to the
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REF
should be