adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet - Page 9
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adc12ds105cisq
Manufacturer Part Number
adc12ds105cisq
Description
Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
Manufacturer
National Semiconductor Corporation
Datasheet
1.ADC12DS105CISQ.pdf
(24 pages)
I
I
t
t
t
Symbol
A
DR
CONV
AD
AJ
Symb
ADC12DS080 Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V
f
amplitude. Boldface limits apply for T
CLK
= 80 MHz, V
Analog Supply Current
Digital Output Supply Current
Power Consumption
Power Down Power Consumption
Maximum Clock Frequency
Minimum Clock Frequency
Conversion Latency
Aperture Delay
Aperture Jitter
CM
= V
Parameter
Parameter
CMO
, C
L
= 5 pF/pin. Typical values are for T
MIN
≤
T
A
≤
Full Operation
Full Operation
In Single-Lane Mode
In Dual-Lane Mode
In Single-Lane Mode
In Dual-Lane Mode
Single-Lane Mode
Dual-Lane, Offset Mode
Dual-Lane, Word Aligned Mode
T
MAX
. All other limits apply for T
9
Conditions
Conditions
A
= 25°C. Timing measurements are taken at 50% of the signal
A
= 25°C (Notes 8, 9)
A
= V
DR
(Note 10)
(Note 10)
Typical
Typical
= +3.0V, Internal V
0.6
0.1
200
845
56
30
Limits
Limits
52.5
7.5
65
80
25
8
9
REF
www.national.com
Clock Cycles
MHz (max)
MHz (min)
mW (max)
mA (max)
= +1.2V,
(Limits)
(Limits)
ps rms
Units
Units
mW
mA
ns