adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet - Page 20

• Manufacturer Part Number: adc12ds105cisq
• Description: Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
• Manufacturer: National Semiconductor Corporation

www.national.com
width requirement for the deasserted pulse - which is
specified in the Electrical Specifications section.
SDI: Serial Data. Must observe setup/hold requirements with
respect to the SCLK. Each cycle is 16-bits long.
R/Wb:
Reserved: Reserved for future use. Must be set to 0.
ADDR:
DATA:
Bits (7:6) Operational Mode
Device Control Register, Address 0h
0 0 Normal Operation.
0 1 Test Output mode. A fixed test pattern
(101001100011 msb->lsb) is sourced at the data
outputs.
1 0 Test Output mode. Data pattern defined by
user in registers 01h and 02h is sourced at data
outputs.
1 1 Reserved.
7 6
OM DLE DCS DF WAM Reserved
A value of '1' indicates a read operation, while a
value of '0' indicates a write operation.
Up to 16 registers can be addressed.
In a write operation the value in this field will be
written to the register addressed in this cycle
when SCSb is deasserted. In a read operation
this field is ignored.
5
4
3
2
1
0
FIGURE 6. Read Timing
FIGURE 7. Write Timing
20
SDO: This output is normally tri-stated and is driven only
when SCSb is asserted. Upon SCSb assertion, contents of
the register addressed during the first byte are shifted out with
the second 8 SCLK falling edges. Upon power-up, the default
register address is 00h.
Bit 5
Bit 4
Bit 3
Data Lane Configuration. When this bit is set to '0',
the serial data interface is configured for dual-lane
mode where the data words are output on two data
outputs (SD1 and SD0) at half the rate of the
single-lane interface. When this bit is set to ‘1’,
serial data is output on the SD1 output only and
the SD0 outputs are held in a high-impedance
state
Duty Cycle Stabilizer. When this bit is set to '0' the
DCS is off. When this bit is set to ‘1’, the DCS is
on.
Data Format. When this bit is set to ‘1’ the data
output is in the “twos complement” form. When
this bit is set to ‘0’ the data output is in the “offset
binary” form.
20211715
20211716