adc12ds105cisq National Semiconductor Corporation, adc12ds105cisq Datasheet - Page 19

• Manufacturer Part Number: adc12ds105cisq
• Description: Dual 12-bit, 105 Msps A/d Converter With Serial Lvds Outputs
• Manufacturer: National Semiconductor Corporation

Functional Description
Operating on a single +3.0 or 3.3V supply, the AD-
C12DS080/105 digitizes two differential analog input signals
to 12 bits, using a differential pipelined architecture with error
correction circuitry and an on-chip sample-and-hold circuit to
ensure maximum performance.
Serial Output Data Format : The digital data for each chan-
nel is provided in a serial format. Two modes of operation are
available for the serial data format. Single-lane serial format
(shown in Figure 2) uses one set of differential data signals
per channel. Dual-lane serial format (shown in Figure 3) uses
two sets of differential data signals per channel in order to
slow down the data and clock frequency by a factor of 2. At
slower rates of operation (typically below 65 Msps) the single-
lane mode may the most efficient to use. At higher rates the
user may want to employ the dual-lane scheme. In either case
DDR-type clocking is used. For each data channel, an over-
range indication is also provided. The OR signal is updated
with each frame of data.
Serial Control Interface
The ADC12DS080/105 has a serial interface that allows ac-
cess to the control registers. The serial interface is a generic
SIGNAL DESCRIPTIONS
SCLK: Used to register the input data (SDI) on the rising
edge; and to source the output data (SDO) on the falling edge.
User may disable clock and hold it in the low-state, as long as
clock pulse-width min spec is not violated when clock is en-
abled or disabled.
FIGURE 5. Serial Interface Protocol
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4-wire synchronous interface that is compatible with SPI type
interfaces that are used on many microcontrollers and DSP
controllers.
The ADC's input clock must be running for the Serial Control
Interface to operate. The SPI interface is enabled when the
SPI_EN (pin 56) signal is asserted high. In this case the direct
control pins have no effect. When this signal is deasserted,
the SPI interface is disabled and the direct control pins are
enabled. Please note that the Power Down function is not
available when the SPI is enabled.
Each serial interface access cycle is exactly 16 bits long. A
register-write can be accomplished in one cycle - with the data
field returning the contents of the register addressed in the
command field of the same cycle. A random access register-
read requires 2 cycles - one to load the address and the
second to read the register addressed in the previous cycle.
Register space supported by this interface is 16, although
only a subset is implemented in this device. Figure 5 shows
the access protocol used by this interface. Each signal's func-
tion is described below. The Read Timing is shown in Figure
6, while the Write Timing is shown in Figure 7
SCSb: Serial Interface Chip Select. Each assertion starts a
new register access - i.e., the SDATA field protocol is re-
quired. The user is required to deassert this signal after the
16th clock. If the SCSb is deasserted before the 16th clock,
no address or data write will occur. The rising edge captures
the address just shifted-in and, in the case of a write opera-
tion, writes the addressed register. There is a minimum pulse-
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