adc16061ccvt National Semiconductor Corporation, adc16061ccvt Datasheet - Page 18

• Manufacturer Part Number: adc16061ccvt
• Description: Self-calibrating 16-bit, 2.5 Msps, 390 Mw A/d Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Applications Information
remedy. The solution is to keep the analog circuitry sepa-
rated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have sig-
nificant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients dur-
ing clock or signal edges, like the 74F and the 74AC(T)
families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Each bypass capacitor should be located as close to the
appropriate converter pin as possible and connected to the
pin and the appropriate ground plane with short traces. The
analog input should be isolated from noisy signal traces to
avoid coupling of spurious signals into the input. Any exter-
nal component (e.g., a filter capacitor) connected between
the converter’s input and ground should be connected to a
very clean point in the ground return.
Generally, analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
To maximize accuracy in high speed, high resolution sys-
tems, however, avoid crossing analog and digital lines alto-
gether. It is important to keep any clock lines isolated from
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18
ALL other lines, including other digital lines. Even the gen-
erally accepted 90 degree crossing should be avoided as
even a little coupling can cause problems at high frequen-
cies. This is because other lines can introduce phase noise
(jitter) into the clock line, which can lead to degradation of
SNR.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, not even with just a small part of their bodies beside
each other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the ground plane. We recommend the
use of a single ground plane. That is, do not split the analog
and digital ground planes. Rather, use a split power plane.
Figure 9 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
and interconnections should be placed in an area reserved
for analog circuitry. All digital circuitry and I/O lines should be
placed in an area reserved for digital circuitry. Violating these
rules can result in digital noise getting into the analog cir-
cuitry, which will degrade accuracy and dynamic perfor-
mance (THD, SNR, SINAD).
All ground connections should have a low inductance path to
ground.