adc16061ccvt National Semiconductor Corporation, adc16061ccvt Datasheet - Page 3

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adc16061ccvt

Manufacturer Part Number
adc16061ccvt
Description
Self-calibrating 16-bit, 2.5 Msps, 390 Mw A/d Converter
Manufacturer
National Semiconductor Corporation
Datasheet

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Analog I/O
No.
Pin Descriptions and Equivalent Circuits
Pin
48
47
50
49
52
51
1
4
V
V
V
V
V
Symbol
REF
REF
REF (MID)
REF
REF
V
V
V
IN
IN
CM
+
+
+
OUT
OUT
IN
IN
Equivalent Circuit
Non-Inverting analog signal Input. With a 2.0V reference voltage
and a 2.0V common mode voltage, V
range is from 1.0 volt to 3.0 Volts.
Inverting analog signal Input. With a 2.0V reference voltage and a
2.0V common mode voltage, V
from 1.0 Volt to 3.0 Volts. The input signal should be balanced for
best performance.
Positive reference input. This pin should be bypassed to AGND
with a 0.1 µF monolithic capacitor. V
a minimum of 1.8V and a maximum of 2.2V. The full-scale input
voltage is equal to V
Negative reference input. In most applications this pin should be
connected to AGND and the full reference voltage applied to V
IN
this pin should be bypassed to AGND with a 0.1 µF monolithic
capacitor. The full-scale input voltage is equal to V
V
Output of the high impedance positive reference buffer. This pin
should be bypassed to AGND with a 0.1 µF monolithic capacitor in
parallel with a 10 µF capacitor.
The output of the negative reference buffer. This pin should be
bypassed to AGND with a 0.1 µF monolithic capacitor in parallel
with a 10 µF capacitor.
Output of the reference mid-point. This pin should be bypassed to
AGND with a 0.1 µF monolithic capacitor. This voltage is derived
from V
Input to the common mode buffer, nominally equal to 40% of the
supply voltage (2.0V). This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. Best performance is obtained if this
pin is driven with a low impedance source of 2.0V.
REF
. If the application requires that V
3
IN
CM
.
.
REF
+
IN
Description
minus V
CM
, the input signal voltage range is
REF
REF
REF
CM
+ minus V
IN
, the input signal voltage
IN
be offset from AGND,
.
REF− IN
REF
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+
IN
should be
minus
REF
+

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