adc16061ccvt National Semiconductor Corporation, adc16061ccvt Datasheet - Page 8

• Manufacturer Part Number: adc16061ccvt
• Description: Self-calibrating 16-bit, 2.5 Msps, 390 Mw A/d Converter
• Manufacturer: National Semiconductor Corporation

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t
t
t
t
t
t
AC Electrical Characteristics
AD
OD
EOCL
ON
OFF
CAL
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND I/O = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
maximum power dissipation will be reached only when the ADC16061 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: See AN450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltages above V
However, errors in the A/D conversion can occur if the input goes above V
input voltage must be ≤4.85V
Note 8: To guarantee accuracy, it is required that V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) with 50% duty cycle clock.
Note 12: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 14: Optimum SNR performance will be obtained by keeping the reference voltage in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), or the
LM4041CIZ-ADJ (TO-92 package), bandgap voltage reference is recommended for this application.
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
PD = +5V, V
for T
Symbol
A
ESD Protection Scheme for Digital Input pins
= T
J
= T
REF +
MIN
Aperture Delay
Falling edge of CLK to Data
Valid
Falling edge of CLK to falling
edge of EOC
RD low to data valid on D00
-D15
RD high to D00 -D15 in
TRI-STATE
Calibration Time
= +2.0V, V
to T
DC
MAX
to ensure accurate conversions
A
= T
: all other limits T
REF
REF IN
Parameter
J
= 25˚C, and represent most likely parametric norms.
JA
= (V
), and the ambient temperature (T
REF
= AGND, f
+) − (V
A
and V
10088911
REF
J
A
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
D
CLK
−) given as +2.0V, the 16-bit LSB is 30 µV.
be connected together and to the same power supply with separate bypass capacitors at each V
= T
(Continued)
= 2.5 MHz, RS = 25Ω, C
J
IL
= 25˚C(Notes 7, 8, 9)
= 0.4V for a falling edge and V
A
A
or below GND by more than 100 mV. As an example, if V
A
), and can be calculated using the formula P
Conditions
or below GND will not damage this device, provided current is limited per Note 3.
8
IN
<
AGND or V
ESD Protection Scheme for Analog Input and Digital
+
L
IN
= V
= 50 pF/pin. After Auto-Cal. Boldface limits apply
IH
>
V
= 2.4V for a rising edge. TRI-STATE output voltage is forced
A
A
or V
(Note 10)
= V
1/(4f
Typical
110
D
50
23
25
D
9
), the current at that pin should be limited to 25 mA.
CLK
= +5.0V, V
Output pins
)
D
MAX = (T
(Note 11)
D
Limits
130
I/O = 3.0V or 5.0V,
38
95
90
33
33
J
max - T
A
is 4.75 V
10088912
A
)/θ
JA
DC
. The values for
ns (max)
ns (max)
ns (max)
ns (max)
, the full-scale
(Limits)
ns (min)
ns (min)
Units
ms
ns
J
max, the
+
pin.