adc16061ccvt National Semiconductor Corporation, adc16061ccvt Datasheet - Page 4

• Manufacturer Part Number: adc16061ccvt
• Description: Self-calibrating 16-bit, 2.5 Msps, 390 Mw A/d Converter
• Manufacturer: National Semiconductor Corporation

www.national.com
Digital I/O
Analog Power
6, 7, 45
5, 8, 46
Digital Power
12, 13,
14, 19,
41, 42,
21-32
35-38
Pin Descriptions and Equivalent Circuits
No.
Pin
10
11
40
18
44
17
20
43
Symbol
CLOCK
RESET
D00-15
AGND
DGND
EOC
CAL
RD
PD
V
V
D
A
Equivalent Circuit
Digital clock input. The input voltage is captured t
the clock signal. The clock frequency should not be changed or
interrupted during conversion or while reading data output.
CAL is a level-sensitive digital input that, when pulsed high for at
least two clock cycles, puts the ADC into the CALIBRATE mode.
See Section 2.3 .
RESET is a level-sensitive digital input that, when pulsed high for
at least 2 CLOCK cycles, results in the resetting of the ADC. This
reset pulse must be applied after ADC power-up, before calibration.
RD is the (READ) digital input that, when low, enables the output
data buffers. When this input pin is high, the output data bus is in a
high impedance state.
PD is the Power Down input that, when low, puts the converter into
the power down mode. When this pin is high, the converter is in
the active mode.
EOC is a digital output that, when low, indicates the availability of
new conversion results at the data output pins.
Digital data outputs that make up the 16-bit TRI-STATE conversion
results. D00 is the LSB, while D15 is the MSB (SIGN bit) of the
two’s complement output word.
Positive analog supply pins. These pins should be connected to a
clean, quiet +5V source and bypassed to AGND with 0.1 µF
monolithic capacitors in parallel with 10 µF capacitors, both located
within 1 cm of these power pins.
The ground return for the analog supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and grounding) for more details).
Positive digital supply pin. This pin should be connected to the
same clean, quiet +5V source as is V
with a 0.1 µF monolithic capacitor in parallel with a 10µF capacitor,
both located within 1 cm of the power pin.
The ground return for the digital supply. AGND and DGND should
be connected together directly beneath the ADC16061 package.
See Section 5 (Layout and Grounding) for more details.
4
(Continued)
Description
A
and bypassed to DGND
AD
after the fall of