tda8757c NXP Semiconductors, tda8757c Datasheet - Page 14

• Manufacturer Part Number: tda8757c
• Description: Tda8757c Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 10111
Preliminary data
8.2.2 Important recommendations
8.2.3 ADCs
8.2.4 Data outputs
A fine correction is also used to finely tune the gain on the three channels and to
compensate the channel-to-channel gain mismatch. The fine correction is done using
the following principle: the three binary codes, stored in the three 5-bit registers
(FINER, FINEG and FINEB) are converted into three analog voltages (with three
DACs) and are independently added to the reference voltage (
different reference voltages are used for the gain calibration of the three channels.
When the COARSE registers are set at full-scale, the resolution of the fine registers
corresponds to
The clamping and the gain calibration requires two external signals (pulses). One
signal is connected to pin CLP and the other is connected to pin HSYNC. It is very
important that:
Three ADCs convert analog signals into three series of 8-bit codes, with a maximum
clock frequency of 205 Msps. The ADCs input range is 1 V (p-p) full-scale and the
pipeline delay is 1 clock cycle from the sampling to the data output. The reference
ladders regulators are integrated.
The ADC outputs are straight binary. It is possible to switch the data and clock
outputs to high-impedance by setting bit PWD in register FINER (PWD = 1 when the
data and clock outputs are in high-impedance). The data and clock outputs can drive
a maximum 10 pF load. The timing must be checked very carefully if the capacitive
load exceeds 10 pF.
It is possible to force the outputs to logic 0 during the gain calibration (during HSYNC
pulse) and during the clamping (CLP pulse). This mode is activated through the serial
interface by setting bit ‘Blk’ to logic 1 in register DEMUX.
The TDA8757C provides outputs either on one port (port A) or on two ports (ports A
and B). The selection is made with the serial interface by setting bit ‘Dmx’ to logic 0 or
logic 1 in register DEMUX. When just one port is used (Dmx = 0), the unused ports
are forced to LOW level. When two ports are used (Dmx = 1), it is possible to select
the port that would provide the odd pixel by setting bit ‘Odda’ to logic 1 or logic 0 in
register DEMUX; when this bit is logic 1, odd pixel on output of port A.
One out-of-range bit exists per channel (OR
when the signal is out-of-range of the ADC voltage ladder.
Finally, two configurations are possible: either the port A outputs and the port B
outputs are both synchronous or they are interleaved. The selection is done by
setting bit ‘Shift’ to logic 0 or logic 1 in register DEMUX.
•
•
The active part of these two signals occur during the blanking of the video signal,
in order not to interrupt or disturb the active video.
The active part of these two signals do not overlap each other, in order to perform
correctly the gain calibration and the clamping. Normally the clamp pulse is sent
after the end of the horizontal synchronization pulse.
1
2
Rev. 01 — 14 August 2002
LSB peak-to-peak (see Equation 3).
R
, OR
G
and OR
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Triple 8-bit ADC 205 Msps
B
). It will be at logic 1
1
TDA8757C
16
V
ref
). Thus, three
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