tda8757c NXP Semiconductors, tda8757c Datasheet - Page 18

• Manufacturer Part Number: tda8757c
• Description: Tda8757c Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4:
9397 750 10111
Preliminary data
Function
name
FINEB
CONTROL X
VCO
DIVIDER
(LSB)
PHASE
DEMUX
I
2
Subaddress
A7 A6 A5 A4 A3 A2 A1 A0 MSB
X
X
X
X
X
C-bus and 3W-bus registers
X
X
X
X
X
X
9.1.1 Subaddress
9.1.2 Offset register
X
X
X
X
X
X
X
X
X
X
X
X
All the registers are defined by a subaddress of 7 bits: bit Mode refers to the mode
which is used with the I
each register.
Bit Mode, used only with the I
Mode 0
Mode 1
The default values correspond to a VESA 1280
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in
Table 5:
Programmed code
0
1
2
...
127
...
254
255
256
...
287
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
Coding
…continued
Each register is programmed independently, by giving its subaddress
and its content.
All the registers are programmed one after the other, by giving this initial
condition (XXX1 1111) as the subaddress state; thus, the registers are
changed following the predefined sequence of 16 bytes (from
subaddress 0000 to 1101).
0
1
0
1
0
1
Bit definition
X
Vlevel Hlevel
Z2
Di8
Di0
Blk
Rev. 01 — 14 August 2002
2
C-bus interface, bits ‘Sa3’ to ‘Sa0’ give the subaddress of
X
Z1
Di7
Ckrs
Shpixel Ckrp
Clamp code
...
0
...
63.5
64
120
...
136
2
63.5
63
62.5
C-bus, allows two modes for the programming:
Cken
Edge
Z0
Di6
Ckext
Fb4
Up
Vco1 Vco0 Di11
Di5
P4
Ckdp Ckdd Shift
Fb3
Do
Di4
P3
1024 at 75 Hz graphic mode.
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Fb2
Ip2
Di3
P2
ADC output
0
...
63 or 64
64
120
...
136
Triple 8-bit ADC 205 Msps
Fb1
Ip1
Di10
Di2
P1
Odda Dmx
TDA8757C
Table
underflow
LSB
Fb0
Ip0
Di9
Di1
P0
5.
Default
value
XX00 0000
0000 0111
1011 1011
0100 1100
0000 0000
1000 0111
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