tda8757a NXP Semiconductors, tda8757a Datasheet - Page 16

• Manufacturer Part Number: tda8757a
• Description: Tda8757a Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09549
Preliminary data
Fig 8. Timing diagram; CKREFO; Dmx = 0.
It is possible to control the phase of the ADC clock (CKADC), through the serial
interface, with the included digital phase-shift controller. The phase register (5 bits)
enables to shift the phase by steps of 11.25 deg.
The CKREF signal is resynchronized by the synchro-block on the CKADC clock. The
new reference is available on pin CKREFO. This synchronization may be done either
with the CKREF signal directly, or with the output of the divider in the PLL (see
Figure
The selection is done via the serial interface by setting bit ‘Ckrs’ in the phase register
(Ckrs = 1 when the CKREF signal is used). The polarity of the signal on pin CKREFO
is controlled through the serial interface by setting bit ‘Ckrp’ in register DEMUX
(positive polarity if Ckrp = 0). The width of this signal is fixed to 8 clock cycles.
The PLL provides also a CKDATA clock. This clock is synchronized on the data
outputs whatever the output mode is.
It is possible to delay the CKDATA clock with a constant time (
the outputs) by setting bit ‘Ckdd’ to logic 1 in register DEMUX. Moreover, it is possible
to reverse the CKDATA clock, referenced to the outputs, by setting bit ‘Ckdp’ in
register DEMUX.
The maximum capacitive load for each clock output is 10 pF.
If an external clock is used, it has to be connected to pin CKEXT. Bit ‘Ckext’ and
bit ‘Ckrs’ in the phase register have to be set at logic 1. Moreover, it is also important
to disconnect the internal PLL by using the following settings:
There is a delay between the input signal on pin CKREF and the corresponding
output on pin CKREFO; see
t
t
t
CKREFO
CKAO
CLK(buffer)
•
•
Set bit ‘Do’ in the control register to logic 1.
Set bits ‘Vco1’ and ‘Vco0’ in register VCO to logic 0.
CKREFO
CKREFO
Ckrp = 0
Ckrp = 1
CKADC
CKREF
= t
3).
= either t
CLK(buffer)
= tbf and t
CKAO
+ t
Rev. 01 — 22 March 2002
phase selector
phase selector
(if clock phase >01000) or t
8 clock periods
Figure
=
---------------
phase
8. This delay is t
2
T
t CKAO
CLK pixel
t CKREFO
CKAO
FCE699
CKREFO
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
+ T
Triple 8-bit ADC 205 Msps
CLK(pixel)
:
TDA8757A
ns, compared to
(if phase <01000)
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