tda8023 NXP Semiconductors, tda8023 Datasheet - Page 11
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tda8023
Manufacturer Part Number
tda8023
Description
Tda8023 Low Power Ic Card Interface
Manufacturer
NXP Semiconductors
Datasheet
1.TDA8023.pdf
(32 pages)
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Quantity
Price
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Manufacturer:
NXP/恩智浦
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Manufacturer:
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NXP Semiconductors
TDA8023_1
Product data sheet
Table 8.
Table 9.
[1]
Bit
3
2
1
0
Bit
7
6
5
4
3 and 2
1 and 0
Synchronous or asynchronous cards management are defined when bit START is set: the TDA8023 will be
in asynchronous cards management when bit RSTIN = 1 when bit START is set to logic 1.
Symbol
PDWN
5V/3VN
WARM
START
Symbol
TEST
RSTIN
C8
C4
CLKPD[2:1]
CLKDIV[2:1]
Command - Register 0 in Write mode bit description
R1_00 - Register 1 subaddress 00 in Read/Write mode bit description
[1]
Description
1: applies on pin CLK the frequency that is defined by bits CLKPD[2:1]
and reduces power consumption (in Synchronous mode); this bit can not
change if bit START is logic 1
1: V
0: V
this bit can not change if bit START is logic 1
1: initiates a warm reset procedure
this bit will be automatically reset by hardware when bit MUTE is set to
logic 1
1: initiates an activation sequence and a cold reset procedure (only if bit
SUPL = 0 and the bit PRES = 1)
0: initiates a deactivation sequence
Description
1: the circuit is in Test mode
0: the circuit is in Operational mode
defines the voltage on pin RST:
1: V
0: 0 V
defines the voltage on pin C8:
1: V
0: 0 V
defines the voltage on pin C4:
1: V
0: 0 V
clock pulse definition:
00: CLK stop LOW
01: CLK stop HIGH
10: frequency on pin CLK: f
11: no change
in Synchronous mode bit CLKPD2 is always logic 0 by hardware and bit
CLKPD1 controls the voltage on pin CLK:
1: V
0: 0 V
clock divider:
00: f
01: f
10: f
11: f
in Synchronous mode, bits CLKDIV[2:1] are always 00 by hardware
Rev. 01 — 16 July 2007
CC
CC
CC
CC
CC
CC
CLK
CLK
CLK
CLK
= 5 V
= 3 V
= f
= f
= f
= f
CLKIN
CLKIN
CLKIN
CLKIN
/ 2
/ 4
/ 5
CLK
= f
osc(int)
/ 2
Low power IC card interface
…continued
TDA8023
© NXP B.V. 2007. All rights reserved.
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