uda1325 NXP Semiconductors, uda1325 Datasheet - Page 42

• Manufacturer Part Number: uda1325
• Description: Universal Serial Bus Usb Codec
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1999 May 10
Analog PLL (for ADC clock)
f
t
Power-on reset
t
PGA and ADC
V
C
(THD + N)/S
S/N
f
OL
clk(PLL)
strt(PO)
su(PO)
s
i(FS)(rms)
ct
i(PGA)
Universal Serial Bus (USB) CODEC
SYMBOL
PLL clock frequency
duty factor
start-up time after power-on
power-on set-up-time
full-scale input voltage (RMS value) PGA gain = 3 dB
input capacitance of the PGA
total harmonic distortion plus
noise-to-signal ratio
signal to noise ratio
crosstalk between channels
sample frequency (128f
digital output level
PARAMETER
s
)
note 1
PGA gain = 0 dB
PGA gain = 3 dB
PGA gain = 9 dB
PGA gain = 15 dB
PGA gain = 21 dB
PGA gain = 27 dB
f
input signal of
1 kHz; PGA
gain = 0 dB;
note 4
V
PGA gain = 0 dB
PGA gain = 0 dB,
V
s
i
i
= 44.1 kHz at
CONDITIONS
V
1.0 V (RMS)
V
= 0.0 V
= 1 V (RMS)
i
i
42
(0 dB)
( 60 dB)
8.1920
25C
90
0.640
MIN.
ref
(2)
11.2896
50
1414
1000
708
355
178
89
44
0.0056
3.2
95
100
85
30
2.0
TYP.
(3)
Preliminary specification
12.2880
10
20
0.01
10.0
7.04
80
20
MAX.
UDA1325
MHz
%
ms
ms
mV
mV
mV
mV
mV
mV
mV
pF
dB
%
dB
%
dBA
dB
MHz
dBFS
UNIT