uda1351h NXP Semiconductors, uda1351h Datasheet - Page 12

• Manufacturer Part Number: uda1351h
• Description: 96 Khz Iec 958 Audio Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.5.3
The digital data interface enables the exchange of digital
data to and from an external signal processing device.
The digital output and input formats are identical by
design. The possible formats are (see Fig.6):
Important: the edge of the WS signal must fall on the
negative edge of the BCK signal at all times for proper
operation of the input and output interface (see Fig.9).
In the static pin control mode the format is selected by
means of pins L3MODE and L3DATA. In the L3 control
mode the format defaults to the I
programmable via the L3 interface.
The IEC 958 decoder provides the pre-emphasis
information from the IEC 958 input bitstream to pins
PREEM0 and PREEM1 and to the L3 interface register.
Controlling the de-emphasis is different for the 2 modes:
8.5.4
The audio feature processor automatically provides
de-emphasis for the IEC 958 data stream in the static pin
control mode and default mute at start-up in the L3 control
mode. When used in the L3 control mode it provides the
following additional features:
2000 Jul 27
I
LSB-justified with a word length of 16 bits
LSB-justified with a word length of 20 bits
LSB-justified with a word length of 24 bits.
Static pin control mode:
– For IEC 958 input de-emphasis is automatically
L3 control mode:
– IEC 958 input: bit SPDSEL must be set to logic 1 and
– I
Volume control using 6 bits
Bass boost control using 4 bits
Treble control using 2 bits
Mode selection of the sound processing bass boost and
treble filters: flat, minimum and maximum
Soft mute control with raised cosine roll-off
De-emphasis selection of the incoming data stream for
f
96 kHz IEC 958 audio DAC
2
s
S-bus with a word length of up to 24 bits
= 32.0, 44.1 and 48.0 kHz.
done, but for I
possible.
de-emphasis is done automatically
de-emphasis can be controlled via bits DE0
and DE1.
2
S-bus input: bit SPDSEL must be set to logic 0 and
D
A
UDIO FEATURE PROCESSOR
IGITAL DATA OUTPUT AND INPUT INTERFACE
2
S-bus input de-emphasis is not
2
S-bus settings and is
12
8.5.5
The UDA1351H includes an on-board interpolating filter
which converts the incoming data stream from 1f
by cascading a recursive filter and a FIR filter.
Table 2 Interpolator characteristics
8.5.6
The third-order noise shaper operates at 128f
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.
8.5.7
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage.
The filter coefficients are implemented as current sources
and are summed at virtual ground of the output operational
amplifier. In this way very high signal-to-noise
performance and low clock jitter sensitivity is achieved.
A post filter is not needed due to the inherent filter function
of the DAC. On-board amplifiers convert the FSDAC
output current to an output voltage signal capable of
driving a line output.
The output voltage of the FSDAC is scaled proportionally
with the power supply voltage.
Pass-band ripple
Stop band
Dynamic range
DC gain
PARAMETER
I
N
F
NTERPOLATOR
ILTER
OISE SHAPER
S
TREAM
CONDITIONS
0f
0f
DAC (FSDAC)
s
s
>0.65f
to 0.45f
to 0.45f
s
s
s
Product specification
UDA1351H
VALUE (dB)
s
115
. It shifts
0.03
3.5
50
s
to 128f
s