uda1351h NXP Semiconductors, uda1351h Datasheet - Page 15

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uda1351h

Manufacturer Part Number
uda1351h
Description
96 Khz Iec 958 Audio Dac
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
8.6.2
The L3 control mode allows maximum flexibility in controlling the UDA1351H.
It should be noted that in the L3 control mode several base-line functions are still controlled by pins on the device and
that on start-up in the L3 control mode the output is explicitly muted by bit MT via the L3 interface.
Also it should be noted that in using the L3 control mode, an initialization string is needed after power-up of the device
for reliable operation.
Table 4 Pin description in the L3 control mode
2000 Jul 27
Mode selection pin
Input pins
Status pins
30 and 42 PREEM1 and
Test pins
96 kHz IEC 958 audio DAC
PIN
35
10
21
23
34
39
44
1
5
6
L3
CONTROL MODE
SELSTATIC
RESET
L3DATA
L3CLOCK
L3MODE
LOCK
PREEM0
TC
TEST1
TEST2
RTCB
NAME
VALUE
00
01
10
11
0
0
1
0
1
0
1
0
0
select L3 control mode; must be connected to V
normal operation
reset
must be connected to the L3-bus
must be connected to the L3-bus
must be connected to the L3-bus
clock regeneration or IEC 958 decoder out-of-lock
clock regeneration and IEC 958 decoder locked
IEC 958 input: no pre-emphasis
IEC 958 input: f
IEC 958 input: f
IEC 958 input: f
must be connected to ground (V
must be connected to supply voltage (V
must be connected to ground (V
must be connected to ground (V
s
s
s
= 32.0 kHz with pre-emphasis
= 44.1 kHz with pre-emphasis
= 48.0 kHz with pre-emphasis
15
SSD
SSD
SSD
FUNCTION
)
)
)
DDD
)
SSD
Product specification
UDA1351H

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