adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet - Page 2

• Manufacturer Part Number: adsp-21371
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371
KEY FEATURES
At 266 MHz (3.75 ns) core instruction rate, the ADSP-21371
1M bit on-chip, SRAM for simultaneous access by the core
4M bit on-chip, mask-programmable ROM
Dual data address generators (DAGs) with modulo and bit-
Zero-overhead looping with single-cycle loop setup, provid-
Single instruction multiple data (SIMD) architecture
Transfers between memory and core at a sustained
INPUT/OUTPUT FEATURES
DMA controller supports:
32-bit wide external port provides glueless connection to
Digital audio interface (DAI) includes eight serial ports, four
Digital peripheral interface (DPI) includes, two timers, one
Eight dual data line serial ports that operate at up to 50 Mbps
TDM support for telecommunications interfaces including
performs 1.596 GFLOPs/533 MMACs
processor and DMA
reverse addressing
ing efficient program sequencing
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
Parallelism in buses and computational units allows:
4.25G bytes/second bandwidth at 266 MHz core instruc-
tion rate
32 DMA channels for transfers between ADSP-21371 inter-
32-bit DMA transfers at peripheral clock speed, in parallel
both synchronous (SDRAM) and asynchronous memory
devices
Programmable wait state options: 2 to 31 SDCLK cycles
Delay-line DMA engine maintains circular buffers in exter-
SDRAM accesses at 133 MHz and asynchronous accesses at
4 memory select lines allows multiple external memory
precision clock generators, an input data port, an S/PDIF
transceiver, and a signal routing unit
UART, and two SPI ports, and a 2-wire interface port
Outputs of PCG’s A and B can be routed through DAI pins
Outputs of PCG's C and D can be driven on to DAI as well as
DPI pins
on each data line — each has a clock, frame sync, and two
data lines that can be configured as either a receiver or
transmitter pair
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
the assembly level
Single cycle executions (with or without SIMD) of a mul-
tiply operation, an ALU operation, a dual memory read
or write, and an instruction fetch
nal memory and a variety of peripherals
with full-speed processor execution
nal memory with tap/offset based reads
44.4 MHz
devices
—
PROCESSOR CORE
Rev. 0 | Page 2 of 48 | June 2007
Up to 16 TDM stream support, each with 128 channels per
Companding selection on a per channel basis in TDM mode
Input data port, configurable as eight channels of serial data
Signal routing unit provides configurable and flexible con-
2 muxed flag/IRQ lines
1 muxed flag/IRQ /MS pin
1 muxed flag/Timer expired line /MS pin
S/PDIF-compatible digital audio receiver/transmitter sup-
Pulse-width modulation provides:
ROM based security features include:
PLL has a wide variety of software and hardware multi-
Newly introduced “Running Reset” feature that allows a reset
Available in 208-lead MQFP package (see
frame
or seven channels of serial data and up to a 20-bit wide
parallel data channel
nections between the various peripherals and the DAI/DPI
components
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I
16-, 18-, 20- or 24-bit word widths (transmitter)
16 PWM outputs configured as four groups of four outputs
supports center-aligned or edge-aligned PWM waveforms
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Page
access under program control to sensitive code
of the processor core and peripherals, but without reset-
ting the PLL and SDRAM controller, or performing a boot
48)
2
S or right-justified serial data input with
Ordering Guide on