adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet - Page 26

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adsp-21371

Manufacturer Part Number
adsp-21371
Description
Sharc Processor
Manufacturer
Analog Devices, Inc.
Datasheet

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ADSP-21371
SDRAM Interface Timing (133 MHz SDCLK)
Table 24. SDRAM Interface Timing
1
2
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
For F
Command pins include: SDCAS, SDRAS, SDWE, MSx, SDA10, and SDCKE.
SSDAT
HSDAT
SDCLK
SDCLKH
SCCLKL
DCAD
HCAD
DSDAT
ENSDAT
CCLK
= 133 MHz (SDCLK ratio = 1:2).
DATA Setup Before SDCLK
DATA Hold After SDCLK
SDCLK Period
SDCLK Width High
SDCLK Width Low
Command, ADDR, Data Delay After SDCLK
Command, ADDR, Data Hold After SDCLK
Data Disable After SDCLK
Data Enable After SDCLK
DATA (IN)
DATA(OUT)
CMND ADDR
SDCLK
(OUT)
1
t
SSDAT
Figure 16. SDRAM Interface Timing for 133 MHz SDCLK
Rev. 0 | Page 26 of 48 | June 2007
2
t
2
DCAD
t
SDCLK
t
t
ENSDAT
HSDAT
t
t
DCAD
HCAD
t
SDCLKL
t
t
SDCLKH
DSDAT
Min
0.58
2.2
7.5
3
3
1.3
1.6
t
HCAD
Max
5.3
5.3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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