adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet - Page 28

• Manufacturer Part Number: adsp-21371
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371
Memory Write
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for ACK, DATA, RD, WR, and strobe
timing parameters only apply to asynchronous access mode.
Table 26. Memory Write
1
2
3
4
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
W = (number of wait states specified in AMICTLx register) × t
H = (number of hold cycles specified in AMICTLx register) x t
ACK delay/setup: System must meet t
The falling edge of MSx is referenced.
Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only applies to asynchronous access mode.
See
DAAK
DSAK
DAWH
DAWL
WW
DDWH
DWHA
DWHD
DATRWH
WWR
DDWR
WDE
Test Conditions on Page 44
ADDRESS
MSx
DATA
ACK
WR
RD
—
Bus Master
ACK Delay from Address, Selects
ACK Delay from WR Low
Address, Selects to WR Deasserted
Address, Selects to WR Low
WR Pulse Width
Data Setup Before WR High
Address Hold After WR Deasserted
Data Hold After WR Deasserted
Data Disable After WR Deasserted
WR High to WR, RD Low
Data Disable Before RD Low
WR Low to Data Enabled
—
for calculation of hold times given capacitive and dc loads.
Bus Master
DAAK
, or t
t
t
DAWL
DAAK
DSAK
t
WDE
, for deassertion of ACK (low). For asynchronous assertion of ACK (high) user must meet t
1, 3
2
Figure 18. Memory Write
1, 2
t
DSAK
4
Rev. 0 | Page 28 of 48 | June 2007
2
SDCLK
S
SDCLK
t
DAWH
Min
t
t
W – 1.3
t
H + 0.15
H + 0.02
t
t
2t
t
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
SDCLK
t
WW
—
– 3.6+ W
– 2.7
– 3.0+ W
– 1.37+ H
– 1.5+ H
– 4.1
t
– 5.1
DDWH
Bus Master
Max
t
W – 7.1
t
SDCLK
SDCLK
t
– 10.1 + W
+ 4.9+ H
DATRWH
t
DWHD
t
t
t
WWR
DWHA
DDWR
DAAK
or t
DSAK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
.