dsp56002fc80 Freescale Semiconductor, Inc, dsp56002fc80 Datasheet - Page 20

• Manufacturer Part Number: dsp56002fc80
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal/Pin Descriptions
Serial Communications Interface Port
1-14
SERIAL COMMUNICATIONS INTERFACE PORT
RXD
PC0
TXD
PC1
SCLK
PC2
Signal Name
Output
Output
Output
Output
Signal
Input
Input
Input
Input
Type
Table 1-10 Serial Communications Interface (SCI+) Signals
or
or
or
Tri-stated Receive Data (RXD)—This input receives byte-oriented data and
Tri-stated Transmit Data (TXD)—This output transmits serial data from
Tri-stated SCI Clock (SCLK)—This signal provides an input or output
during
Reset
State
transfers the data to the SCI receive shift register. Input data can be
sampled on either the positive edge or on the negative edge of the
receive clock, depending on how the SCI control register is
programmed.
Port C GPIO 0 (PC0)—This signal is a GPIO signal called PC0
when the SCI RXD function is not being used.
After reset, the default state is GPIO input.
the SCI transmit shift register. In the default configuration, the
data changes on the positive clock edge and is valid on the
negative clock edge. The user can reverse this clock polarity by
programming the SCI control register appropriately.
Port C GPIO 1 (PC1)—This signal is a GPIO signal called PC1
when the SCI TXD function is not being used.
After reset, the default state is GPIO input.
clock from which the receive or transmit baud rate is derived in
the Asynchronous mode, and from which data is transferred in
the Synchronous mode. The direction and function of the signal
is defined by the RCM bit in the SCI+ Clock Control Register
(SCCR).
Port C GPIO 2 (PC2)—This signal is a GPIO signal called PC2
when the SCI SCLK function is not being used.
After reset, the default state is GPIO input.
DSP56002/D, Rev. 3
Signal Description
MOTOROLA