dsp56002fc80 Freescale Semiconductor, Inc, dsp56002fc80 Datasheet - Page 58

• Manufacturer Part Number: dsp56002fc80
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
External Bus Synchronous Timing
2-32
Notes:
No.
163 BR Deassertion to
164 First CKOUT transition
165 First CKOUT transition
170 EXTAL to CKOUT with
171 Second CKOUT
172 Second CKOUT
second CKOUT
transition for
Minimum Timing
to BG Assertion
to BG Deassertion
PLL Disabled
EXTAL to CKOUT
PLL Enabled and
MF < 5
transition to BN
Assertion
transition to BN
Deassertion
1.
2.
3.
4.
5.
Characteristics
If wait states are also inserted using the BCR and if the number of wait states is greater than 2, then
specification numbers T156 and T157 can be increased accordingly.
BS deassertion to address invalid indicates the time after which the address are no longer guaranteed to
be valid.
The minimum number of wait states when using BS/WT is two (2).
For read-modify-write instructions, the address lines will not change states between the read and the
write cycle. However, BS will deassert before asserting again for the write cycle. If wait states are
desired for each of the read and write cycle, the WT pin must be asserted once for each cycle.
When EXTAL frequency is less than 33 MHz, then timing T170 is not guaranteed for a period of 1000
T
C
after PLOCK assertion following the events below:
• when enabling the PLL operation by software,
• when changing the Multiplication Factor,
• when recovering from the Stop state if the PLL was turned off and it is supposed to turn, on
• when exiting the Stop state.
5
Table 2-14 Bus Strobe/Wait Timing (Continued)
with
Min
0.3
—
—
—
—
8
3
40 MHz
DSP56002/D, Rev. 3
Max
T
8.8
5.3
9.7
3.7
5.7
5
C
Min
0.3
—
—
—
—
8
3
66 MHz
Max
T
8.8
5.3
9.7
3.7
5.7
5
C
Min
0.3
—
—
—
—
8
3
80 MHz
MOTOROLA
Max
T
8.8
5.3
9.7
3.7
5.7
5
C
Unit
ns
ns
ns
ns
ns
ns
ns