dsp56002fc80 Freescale Semiconductor, Inc, dsp56002fc80 Datasheet - Page 63
dsp56002fc80
Manufacturer Part Number
dsp56002fc80
Description
24-bit Digital Signal Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56002FC80.pdf
(110 pages)
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MOTOROLA
Notes:
Num
250B
251
(Output)
(Input)
DSCK
(Input)
DSO
1.
2.
DR
DR Assertion Width to Recover from Stop state and
enter Debug mode
DR Assertion to DSO (ACK) Valid (enter Debug
mode) after recovery from Stop state
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:
During this stabilization period, T
varies, a delay of 75,000 T
programs. While it is possible to set OMR bit 6 = 1 when using the internal crystal oscillator, it is not
recommended and these specifications do not guarantee timings for that case.
The maximum specified is periodically sampled and not 100% tested.
•
•
•
•
•
•
• after power-on Reset, and
• when recovering from Stop mode.
Stable External Clock,OMR Bit 6 = 0
Stable External Clock,OMR Bit 6 = 1
Stable External Clock,PCTL Bit 17= 1
Stable External Clock, OMR Bit 6 = 0
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17= 1
1
Characteristics
Figure 2-28 OnCE Acknowledge Timing
Figure 2-27 OnCE Serial Clock Timing
Table 2-15 OnCE Port Timing
C
is typically allowed to assure that the oscillator is stable before executing
233
DSP56002/D, Rev. 3
C
, T
1
230
H
, and T
L
will not be constant. Since this stabilization period
232
(ACK)
65549T
65553T
21T
14T
25T
18T
Min
C
C
C
C
C
+ T
+ T
C
+ T
+ T
231
+ T
+ T
L
L
L
L
L
L
OnCE Port Timing
Max
—
—
—
—
—
—
Specifications
AA0399
AA0400
Unit
ns
ns
ns
ns
ns
ns
2-37
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