saa7142hl NXP Semiconductors, saa7142hl Datasheet
saa7142hl
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saa7142hl Summary of contents
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... Rev. 01 — 16 January 2006 1. General description The SAA7142HL is a combination of two stand-alone multi-standard video decoders. The SAA7142HL is a pure 3 tolerant inputs and I/Os) Complementary Metal-Oxide Semiconductor (CMOS) circuit and a highly integrated circuit for video surveillance applications. Both video decoders are based on the principle of line-locked ...
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... Product data sheet 2 C-bus controlled and share one format (8-bit) on Video Parallel Output (VPO Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 2 C-bus interface (full © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Ordering information Table 2: Ordering information Type number Package Name SAA7142HL LQFP128 9397 750 15208 Product data sheet Conditions Description plastic low profile quad flat package; 128 leads; body 14 Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Min Typ Max 3.0 3.3 3.6 3.1 3.3 3 ...
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... PROCESSING AGND_B CONTROL CONTROL AD1 AI12_B AI1D_B ANALOG-TO- AI11_B DIGITAL CONVERSION AND ANALOG PROCESSING Fig 1. Block diagram of SAA7142HL. 9397 750 15208 Product data sheet MULTISTANDARD TEXT SLICER VBI DATA BYPASS UPSAMPLING FILTER BYPASS UV CHROMINANCE CVBS CIRCUIT AND BCS Y Y LUMINANCE CVBS ...
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... not connect; leave open 17 do not connect; leave open 18 analog supply voltage for the internal CGC of video decoder A Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 102 65 001aad236 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... VPO4 of video decoder B 57 digital video output bus signal VPO3 of video decoder B 58 ground for digital core Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 2 C-bus) for instances A and B 2 C-bus) for instances A and B © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... V) 97 ground for digital pad ring 98 do not connect; leave open 99 do not connect; leave open Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor [1] [1] [1] [1] [1] [2] [3] © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Figure 8) show more details of the AGC. The influence of supply Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 3. During the vertical blanking period, gain C-bus) the static gain levels for the analog © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... V DDA1(DECA) 6 AGND_A LUM This is valid for decoder A and B. Here an example for decoder A is shown. Fig 6. Analog input processing using the SAA7142HL as differential front-end with 9-bit ADC (continued in Figure 10). 9397 750 15208 Product data sheet mgl065 Fig 5. Automatic gain range. ANALOG ...
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... GAIN ACCUMULATOR (18 BITS system variable AGV FGV > GUDL; GUDL = gain update level (adjustable); VBLK = vertical blanking pulse; HSY = horizontal sync pulse; AGV = actual gain value; FGV = frozen gain value. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor gain 9 DAC 8 LUMA/CHROMA DECODER ...
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... CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse. and the values 1 (minimum) and 254 (maximum) to fulfil ITU-R BT 601 B R Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 0 GAIN -> HSY SBOT ...
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... The resulting signals are fed to the variable Y-delay compensation and the output interface, which contains the VPO formatter and the output control logic; see 9397 750 15208 Product data sheet Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Figure 10. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... Product data sheet (1) 6 (2) ( 0.54 1.08 Transfer characteristics of the chrominance low-pass dependent on CHBW[1:0] settings. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor mgd147 (4) (1) (3) (2) 1.62 2.16 2.7 f (MHz) © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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LUM CHR 121 TRST_N QUADRATURE 120 TCK TEST DEMODULATOR 117 CONTROL TDI 119 BLOCK TMS 118 TDO SUBCARRIER RESET GENERATION HUEC POWER- DDA0(DECA) CONTROL CSTD[2:0] CLOCK LUM This is valid for decoder A and B. Here an example ...
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... C-bus subaddress 09h, see Figure 17 (1) 6 (2) (4) ( frequencies. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Table 33) in two band-pass Figure 11 mgd139 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2006. All rights reserved. to Figure 16. ...
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... Y 6 (1) (2) (3) ( (1) (2) (4) ( frequencies. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor mgd140 (4) (3) (2) ( (MHz) Y mgd141 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Y 6 (1) (2) (4) ( frequencies (1) (2) ( Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor mgd144 (1) (2) (4) ( (MHz) Y mgd145 (4) (3) (2) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Fig 16. Luminance control, 3.58 MHz trap, prefilter off, different aperture band-pass center 9397 750 15208 Product data sheet (1) (2) ( frequencies. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor mgd146 (1) (2) (4) ( (MHz) Y © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... DETECTOR COARSE AUFD HSB[7:0] HTC[1:0] HSS[7:0] HPLL FIDT FSEL HLCK HTC[1:0] LOOP COUNTER FILTER Figure Figure 18. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Y STAGE CLOCK CIRCUIT CLOCKS LINE-LOCKED CLOCK GENERATOR CLOCK DAC GENERATION CIRCUIT DISCRETE CRYSTAL TIME CLOCK OSCILLATOR ...
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... Product data sheet f (50 Hz (60 Hz). H Clock frequencies ZERO BAND PASS CROSS FC = LLC/4 DETECTION DETECTION Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Frequency (MHz) 24.576 27 13.5 6.75 3.375 PHASE LOOP OSCILLATOR FILTER DIVIDER DIVIDER 1/2 supply voltages will start the reset ...
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... VPO7 to VPO0, SDA and LLC are in high-impedance state LLC and SDA become active; VPO7 to VPO0, are held in high-impedance state VPO7 to VPO0, are held in high-impedance state Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor POC V DDA0 DD DIGITAL POC POC RES_N LOGIC ...
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... Japtext 5 programmable Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 2 C-bus in 2 C-bus subaddresses 41h to 57h Section 8.10. To adjust the slicers WST625 always CC625 VPS WSS WST525 always ...
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... CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved US NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor (MHz) Section 9, subaddresses 41h to 57h). Output 2 ...
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... Format and nominal levels are given in and Table 30, Table 31 Figure 22 and Table 18. 20. Table 27). Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Table 14 signal, 720 active pixels per B R Figure 21 and Table -C data as in active video, with two ...
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... SAV EAV P[3:0] reserved; evaluation not recommended (protection bits according to ITU-R BT 656 formats (data types 15 and 6) every clock cycle within this range R Table 16. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Table 9 and Table 10 Table 9 and Table 10 Figure 22) ...
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... Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor OFTS1 = 0; OFTS0 = 1 OFTS1 = 1; OFTS0 = 0 VRLN = 0 VRLN = according to selected data type 1 1 via LCR2 to LCR24 1 1 (subaddresses 41h to 57h): data types 14 data ...
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Table 11: Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset VOFF8 to VOFF0 = 00Ah; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 1 Line number (1st ...
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Table 14: Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset VOFF8 to VOFF0 = 007h; horizontal pixel offset HOFF10 to HOFF0 = 354h, FOFF = 1, FISET = 0 Line number (1st ...
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... C – 128 + 128 output range. B white black black shoulder sync bottom 001aac244 Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 255 240 212 128 C -COMPONENT 001aac480 C-bus bytes BRIG, CONT and SATN output range. R ...
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... DC Dword count: NEP but does not represent any relevant information for SAA7142HL applications. DC describes the number of succeeding 32-bit words n), where (the two data identification bytes IDI1 and IDI2) and n = number of decoded 4 bytes according to the chosen text standard ...
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... EP , bits Table 8 to Table 10 2. ACK-s SUBADDRESS ACK-s SUBADDRESS ACK-s (n bytes + acknowledge) Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor ACK-s ACK-s DATA data transferred (n bytes + acknowledge) ACK-s DATA ACK-m P data transferred mhb340 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... Slave address R ACK-s ACK-m Subaddress Data Least Significant Bit (LSB) slave address [1] The SAA7142HL supports the fast mode I [2] If more than one byte DATA is transmitted the subaddress pointer is automatically incremented. 2 9.2 I C-bus register description Table 23: Subaddress Description 00h 01h to 04h ...
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Table 24: I C-bus receiver/transmitter overview Register function Subaddress Chip version (read only) 00h Increment delay 01h Analog control 1 02h Analog control 2 03h Analog control 3 04h Reserved 05h Horizontal sync begin 06h Horizontal sync stop 07h ...
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Table 24: I C-bus receiver/transmitter overview Register function Subaddress Horizontal offset 59h Vertical offset 5Ah Horizontal offset [Most Significant Bits 5Bh (MSBs)], vertical offset (MSB) and field offset For testability 5Ch Reserved 5Dh Sliced data identification code 5Eh Reserved ...
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... LSB LSB MODE[3:0] channel input selector 0000 = select CVBS (automatic gain) from AI11; see 0001 = select CVBS (automatic gain) from AI12; see XXXX = reserved; see Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor ID06 ID05 CV2 CV1 IDEL2 IDEL1 ...
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... MODE[3: gain is user programmable via GAI1 - not used; has to be set to logic 0 GAI18 sign bit of gain control; see Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor ADC 001aab319 Table 29 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor GAI13 GAI12 GAI11 GAI10 HSB3 HSB2 HSB1 HSB0 0 ...
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... MHz; see 11 = center frequency is 2.9 MHz; see 9397 750 15208 Product data sheet Figure 11 to Figure 16 Table note 1 Table note 1 Table note 1 Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... CONT6 CONT5 CONT4 Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor BRIG3 BRIG2 BRIG1 BRIG0 CONT3 CONT2 CONT1 CONT0 ...
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... Control bits HUEC7 HUEC6 HUEC5 HUEC4 Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor SATN3 SATN2 SATN1 HUEC3 HUEC2 HUEC1 ...
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... Product data sheet …continued 2/LLC 2/LLC 2/LLC 2/LLC Table 41 2/LLC 2/LLC 2/LLC Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 60 Hz Table 9 and Table 10 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... B R decoder bypassed R [1] Table 44 Figure 25). Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor VREF 625 lines 0 286 first last first 24 309 23 337 622 336 Table 44 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... HUNT_N amplitude searching 0 = amplitude searching active (default amplitude searching stopped 3 - not used; has to be set to logic 0 9397 750 15208 Product data sheet Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Bit field 1 field 2 Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Bit Bit [1] DT3 to DT0 DT3 to DT0 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 ...
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... Sliced data identification code - bit description Symbol Description - not used; have to be set to logic 0 SDID[5:0] sliced data identification code; SDID[5:0] = 000000 (default) Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Table 50 Table 49 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... I C-bus start set-up The given values force the following behavior of the SAA7142HL: • The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active • Automatic field detection enabled, PAL BDGHI or NTSC M standard expected • ...
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... FISET, HAM_N, FCE, HUNT_N, X, CLKSEL[1:0], X FC[7:0] HOFF[7:0] VOFF[7:0] FOFF VOFF8, X, HOFF[10: SDID[5:0] Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Values (binary) Start (hexadecimal read only ...
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... V SSA(all) SS(all) human body model machine model Conditions in free air Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Values (binary) Start (hexadecimal read only read only Min ...
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... for normal video levels 1 V (p-p), termination 18/56 and AC coupling required; coupling capacitor = 47 nF clamping current off MHz i CVBS inputs with different line frequencies Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Min Typ Max 3.0 3.3 3.6 - 125 165 3.1 3.3 3.5 - 210 250 - 1 ...
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... [1] Figure Figure 26 LLC / LLC L nominal frequency 50 Hz field 60 Hz field PAL BGHIN NTSC M; NTSC Japan PAL M combination-PAL N Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Min Typ Max 2 0.4 0.5 - +0.4 2.4 ...
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... With amplifier and anti-alias filter 9397 750 15208 Product data sheet = 25 C; unless otherwise specified. amb Conditions 3rd harmonic , t OHD;DAT PD Typical analog delay AI22 -> ADC(in) (ns Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Min Typ Max 400 - - - 24.576 - - - ...
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... See Fig 27. Horizontal timing diagram. 9397 750 15208 Product data sheet LLC t LLCH t OHD;DAT VPO 28 1/LLC 157 1/LLC Table 59. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor t LLC t LLCL burst burst processing delay CVBS- VPO sync clipped © ...
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... AGND AGND 3.3 V analog digital Do not connect pins 14, 16, 17 25, 27, 36 45, 48, 49 68, 71, 72 79, 82, 83 90, 92, 94, 95 103 and 122 to 128. Fig 28. Application diagram of SAA7142HL. AGND AGND C19 C21 DGND DGND 100 nF ...
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... Philips Semiconductors 15.1 Recommended printed-circuit board layout The SAA7142HL consists of analog and digital areas. Due to this special care needs to be taken for design of layout regarding crosstalk by analog and digital supply interaction recommended to use four layer Printed-Circuit Board (PCB). Top and bottom layer for signal wires, one for ground plane and one for supply plane ...
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... Philips Semiconductors 16. Test information 16.1 Boundary scan test The SAA7142HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7142HL follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture” ...
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... Product data sheet Figure MSB TDI nnnn 0001010110100000 4-bit 16-bit part number version code Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 30. LSB 00000010101 11-bit manufacturer identification 001aad239 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. TDO ...
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... scale (1) ( 0.27 0.20 20.1 14.1 22.15 16.15 0.5 0.17 0.09 19.9 13.9 21.85 15.85 REFERENCES JEDEC JEITA MS-026 Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor detail ...
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... Product data sheet 2 called small/thin packages. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor 3 350 mm so called © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN.. measured in the atmosphere of the reflow oven. The package Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] ...
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... Release date SAA7142HL_1 20060116 9397 750 15208 Product data sheet Data sheet status Change notice Product data sheet - Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor Doc. number Supersedes 9397 750 15208 - © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of Koninklijke Philips Electronics N.V. Rev. 01 — 16 January 2006 SAA7142HL Dual video input processor © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Subaddress 0Bh . . . . . . . . . . . . . . . . . . . . . . . 40 9.3.12 Subaddress 0Ch . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.13 Subaddress 0Dh . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.14 Subaddress 0Eh . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.15 Subaddress 0Fh . . . . . . . . . . . . . . . . . . . . . . . 42 9.3.16 Subaddress 10h . . . . . . . . . . . . . . . . . . . . . . . 42 9.3.17 Subaddress 11h . . . . . . . . . . . . . . . . . . . . . . . 43 9.3.18 Subaddress 13h . . . . . . . . . . . . . . . . . . . . . . . 43 SAA7142HL Dual video input processor 9.3.19 Subaddress 1Fh (read-only register 9.3.20 Subaddress 40h . . . . . . . . . . . . . . . . . . . . . . . 44 9.3.21 Subaddresses 41h to 57h . . . . . . . . . . . . . . . 45 9.3.22 Subaddress 58h . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.23 Subaddresses 59h and 5Bh 9.3.24 Subaddresses 5Ah and 5Bh . . . . . . . . . . . . . 46 9.3.25 Subaddress 5Bh ...