saa7142hl NXP Semiconductors, saa7142hl Datasheet - Page 33

• Manufacturer Part Number: saa7142hl
• Description: Saa7142hl Dual Video Input Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 15208
Product data sheet
9.2 I
Table 22:
[1]
[2]
Table 23:
Code
S
Sr
Slave address W
Slave address R
ACK-s
ACK-m
Subaddress
Data
P
X = Least Significant
Bit (LSB) slave
address
Subaddress Description
00h
01h to 04h
05h
06h to 11h
12h
13h
14h to 1Eh
1Fh
20h to 3Fh
40h to 5Bh
5Ch
5Dh
5Eh
5Fh
60h to 62h
63h to FFh
2
C-bus register description
The SAA7142HL supports the fast mode I
If more than one byte DATA is transmitted the subaddress pointer is automatically incremented.
Description of I
Register subaddresses map
chip version
front-end part
reserved
decoder part
reserved
decoder part
reserved
video decoder status byte
reserved
general purpose data slicer
for testability
reserved
sliced data identification code
reserved
general purpose data slicer status read only
reserved
Rev. 01 — 16 January 2006
Description
START condition
repeated START condition
0100 1010 (= 4Ah) for decoder core B
0100 1000 (= 48h) for decoder core A
0100 1011 (= 4Bh) for decoder core B
0100 1001 (= 49h) for decoder core A
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte; see
data byte; see
STOP condition
read/write control bit; X = 0, order to write (the circuit is slave receiver);
X = 1, order to read (the circuit is slave transmitter)
2
C-bus format
Table 24
2
C-bus specification extension (data rate up to 400 kbit/s).
[1]
Table 24
and
Access
read only
read and write
-
read and write
-
read and write
-
read only
-
read and write
-
-
read and write
-
-
Table note 2
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Reference
Section 9.3.1
Section 9.3.2
-
Section 9.3.6
-
Section 9.3.18
-
Section 9.3.19
-
Section 9.3.20
Section 9.3.25
-
-
Section 9.3.26
-
Section 9.3.27
Section 9.3.28
-
Dual video input processor
SAA7142HL
to
to
to
and
Section 9.3.5
Section 9.3.17
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