saa7199b NXP Semiconductors, saa7199b Datasheet - Page 13

• Manufacturer Part Number: saa7199b
• Description: Digital Video Encoder Denc Genlock-capable
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 7 Function of registers bits of Table 6
1996 Sep 27
Index 00 VTBY
FMT2 to FMT0
SCBW
CCIR
MOD1 to MOD0
Index 01
TRER7 to TRER0
Index 02
TREG7 to TREG0
Index 03
TREB7 to TREB0
Index 04
SYSEL1 to SYSEL0
SCEN
VTRC
NINT
HPLL
OEF
HLCK
Index 05
GDC5 to GDC0
Index 06
IDEL7 to IDEL0
Index 07
PSO7 to PSO0
Index 08 DD
KEYE
SRCC
CPR
COKI
IM
GPSW
SRSN
Index 09 BAME
MPKC1 to MPKC0
Digital Video Encoder (DENC)
GENLOCK-capable
BIT
video look-up table by-pass: 0 = not bypassed; 1 = bypassed (logically OR-ed with MPK)
input formats see Table 8
chrominance bandwidth: 0 = enhanced; 1 = standard
select level: 0 = DMSD2 levels; 1 = CCIR levels
select mode see Table 9
test register red (read/write via MPU-bus; write only via I
test register green (read/write via MPU-bus; write only via I
test register blue (read/write via MPU-bus; write only via I
sync select see Table 10
sync/clamping (HSY/HCL) enable: 0 = disabled (set to HIGH); 1 = enabled
select TV/VTR mode: 0 = TV mode (slow); 1 = VTR mode (fast)
select interlace of encoded signal: 0 = interlaced (262.5/262.5 or 312.5/312.5);
1 = non-interlaced (262/262 or 312/312 in modes 1 and 3 only)
select horizontal lock: 0 = lock enabled; 1 = lock disabled (crystal reference)
status bit field organization (to be read): 0 = even field; 1 = odd field
status bit sync indication (to be read): 0 = locked to external sync; 1 = external sync lost
GENLOCK delay compensation; note 1: data 00 to 3F equals timing of CVBS output signal
which is (46
(t
designated for propagation delay of external GENLOCK source, Fig.10).
increment delay: update of line-locked clock frequency (Table 6, data ‘43’ hex recommended)
Phase sync in output signal, note 1: data 00 to 3F equals to active slope of HSN, VSN/CSYN is
(58
PSO = 58; t
digital video encoder disable: 0 = enabled; 1 = disabled
keying enable: 0 = disabled; 1 = enabled (logically AND-connected with KEY)
clock source: 0 = external system clock; 1 = DTV2 system clock
clock phase reference: 0 = LDV is input (pin 20); 1 = LDV is not
colour-killer: 0 = colour on; 1 = colour off (subcarrier is switched off)
interrupt mask: 1 = interrupt not masked at sync lost (pin 58) 0 = interrupt masked at sync lost
(pin 58)
general purpose switch at bit RTIN = 1: 0 = pin 57 LOW; 1 = pin 57 HIGH
software reset: 0 = no reset; 1 = reset (see “Reset” procedure)
Burst amplitude indication: 0 = burst amplitude measurement is overridden; colour lock always
assumed; 1 = burst amplitude is used to control the CLCK status bit, recommended for
reference signal without subcarrier burst (pure black and white) in order to avoid PLL hunting.
multipurpose key control: with MKP = LOW (pin 32) all functions are as given by software
programming; MKP = HIGH sets in real time with respect to PDn (7 to 0); functions see Table 11
REF1
PSO) pixel clocks = t
corresponds to the falling edge of the horizontal sync pulse of CVBS input signal; t
Rint
GDC) pixel clocks = t
is designated for pipeline delay of the feeding RAM interface, Fig.10).
Rint
earlier with respect to reference point t
13
ofs
earlier with respect to reference point t
FUNCTION
2
C-bus)
2
C-bus)
2
C-bus)
REF2
(t
REF2
Product specification
SAA7199B
REF1
corresponds to
.
ofs
is