admc201 Analog Devices, Inc., admc201 Datasheet
admc201
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admc201 Summary of contents
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... PLCC Package Single Power Supply Industrial Temperature Range GENERAL DESCRIPTION The ADMC201 is a motion coprocessor that can be used with either microcontrollers or digital signal processors (DSP). It provides the functionality that is required to implement a digital control system typical application, the DSP or micro- ...
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... Tested with PWM Switching Frequency of 25 kHz. Specifications subject to change without notice 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz – +85 C unless otherwise noted) A ADMC201AP Units 1 11 Bits ± 2 LSB max ± 2 LSB max ± 5 LSB max ...
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... NOTE 1 All WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states). Number Symbol 25 t rdb_data dly 26 t rdb_data _pio pwh 28 t _pio pwl 1 2 CLK Figure 1 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... –5– ADMC201 Description O/P Internal 2.5 V Analog Reference SUP +5 V Digital Power Supply GND Digital Ground GND Digital Ground GND Digital Ground GND Digital Ground SUP +5 V Digital Power Supply ...
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... Sample and Hold After powering up the ADMC201, bring the RESET pin low for a minimum of two clock cycles in order to enable A/D conversions. Before initiating the first conversion (CONVST) after a reset, the SHA time of 20 system clock cycles must occur. A conversion is initiated by bringing CONVST high for a minimum of one system clock cycle ...
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... PWM TIMER BLOCK OVERVIEW The PWM timers have 12-bit resolution and support program- mable pulse deletion and deadtime. The ADMC201 generates three center-based signals A, B and C based upon user-supplied duty cycles values. The three signals are then complemented and adjusted for programmable deadtime to produce the six outputs ...
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... Vd and Vq voltage signals in the rotor reference frame to three-phase voltage signals ( the stator ref- erence frame. These are then scaled by the processor and written to the ADMC201’s PWM registers in order to drive the inverter. The figures below illustrate the Clarke and Park Transformations respectively. ...
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... The PIODATA register is used to write to and read from the digital I/O port. Bits 0–5 of the PIODATA register correspond to PIO 0–5 on the ADMC201. Bits 6–11 of PIODATA are un- used and always contain 0. Read from PIODATA to determine the state of PIO 0–5. Write to PIODATA to change the states of PIO 0– ...
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... The SGND pin DD (32) and both AGND pins (27, 28) should be star point con- nected at a point close to the AGND pins of the ADMC201. The DGND pins (20, 40, 41, 42, 43, 46, 56, 57, 58) should also be connected to AGND pins close to the ADMC201. ...
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... MHz TMS320C25-50 will derive a 12.5 MHz CLKOUT1 for use by the ADMC201. Note: a pull-up resistor is required on the IRQ (Pin 18) output from the ADMC201. The STOP (Pin 47) must be tied low if not in use. DESCRIPTION OF THE REGISTERS All unspecified register locations are reserved. ...
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... ADMC201 Name RHO PHIP1/VD PHIP2/VQ PHIP3 RHOP PWMTM PWMCHA PWMCHB PWMCHC PWMDT PWMPD PIOCTRL PIODATA SYSCTRL Name ID/PHV1/VX IQ/PHV2 IX/PHV3 IY/VY ADCV ADCW ADCAUX ADCU PIODATA SYSCTRL SYSSTAT Table III. Write Registers Register Function Load RHO (ρ) and Start Reverse Transform ...
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... LOW until the SYSSTAT register is read. Bit 10 If Bit 10 is set to 1, then the reverse Park transforma- tion will be formed in 3/3 mode. For Forward transformations, this bit must be set to 1. –13– ADMC201 Mode Two-/Three-Phase Two-/Three-Phase Three-/Three-Phase Three-/Three-Phase ...
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... Vector Transformation is completed and the Vector Transformation completion interrupts have been enabled. Bit 4 This bit is set to 1 when the rotation results are valid reading this. Bit 11 If any interrupt source on the ADMC201 occurs, then this bit is set Table IX. Programmable Digital I/O Control Register (PIOCTRL) RESET ...
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... DOWN 0.954 (24.23) 0.950 (24.13) REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Plastic Leaded Chip Carrier (P-68A) 0.175 (4.45) 0.169 (4.29 0.050 (1.27) TYP 0.925 (23.50) 0.895 (22.73) 0.019 (0.48) 0.017 (0.43) 0.029 (0.74) 0.027 (0.69 0.104 (2.64) TYP –15– ADMC201 PIN 1 IDENTIFIER BOTTOM VIEW (PINS UP) ...