admc201 Analog Devices, Inc., admc201 Datasheet - Page 2

• Manufacturer Part Number: admc201
• Description: Motion Coprocessor
• Manufacturer: Analog Devices, Inc.

ADMC201–SPECIFICATIONS
Parameter
ANALOG-TO-DIGITAL CONVERTER
ANALOG INPUTS
TRACK AND HOLD
REFERENCE INPUT
REFERENCE OUTPUT
LOGIC
12-BIT PWM TIMERS
VECTOR TRANSFORMATION
EXTERNAL CLOCK INPUT
INTERNAL SYSTEM CLOCK
POWER SUPPLY CURRENT
NOTES
1
2
Specifications subject to change without notice.
Measurements made with external reference.
Tested with PWM Switching Frequency of 25 kHz.
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
Bias Offset Match
Full-Scale Error
Full-Scale Error Match
Conversion Time/Channel
Signal-to-Noise Ratio (SNR)
Channel-to-Channel Isolation
Input Voltage Level
Analog Input Current
Input Capacitance
Aperture Delay
Aperture Time Delay Match
SHA Acquisition Time
Droop Rate
Voltage Level
Reference Input Current
Voltage Level
Voltage Level Tolerance
Drive Capability
V
V
V
V
Input Leakage Current
Three-State Leakage Current
Input Capacitance
Resolution
Programmable Deadtime Range
Programmable Deadtime Increments
Programmable Pulse Deletion Range
Programmable Deletion Increments
Minimum PWM Frequency
Radius Error
Angular Error
Reverse Transformation Time
Forward Transformation Time
Range
Range
I
DD
IL
IH
OL
OH
Two-/Three-Phase Mode
Three-/Three-Phase Mode
2
1
ADMC201AP
11
± 2
± 2
± 5
4
± 6
4
40
60
–58
–55
0–5
100
10
200
20
20
5
2.5
50
2.5
± 5
± 200
0.8
2.0
0.4
4.5
1
1
20
12
0–10.08
2
0–10.16
1
1.5
0.7
30
37
40
6.25–25
6.25–12.5
20
(V
T
A
DD
= –40 C to +85 C unless otherwise noted)
= +5 V
Units
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
System CLK Cycles
dB min
dB max
dB max
Volts
µA max
pF typ
ns max
ns max
System CLK Cycles
mV/ms max
V dc
µA max
Volts
% max
µA max
V max
V min
V max
V min
µA max
µA max
pF typ
Bits
µs
System CLK Cycles
µs
System CLK Cycle
kHz
% max
arc min max
System CLK Cycles
System CLK Cycles
MHz
MHz
mA max
–2–
5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = 12.5 MHz;
Conditions/Comments
Twos Complement Data Format
Integral Nonlinearity
Any Channel
Between Channels
Any Channel
Between Channels
f
Sine Wave Applied to Unselected Channels
Any Channel
Between Channels
Full Load
I
I
160 ns
80 ns
Resolution Varies with PWM Switching Frequency
(10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits,
quencies are Available with Lower Resolution
Park & Clarke Transformation
If > 12.5 MHz, Then It Is Necessary to Divide Down
via SYSCTRL Register
IN
5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Fre-
SINK
SOURCE
= 600 Hz Sine Wave, f
= 400 µA, V
= 20 µA, V
DD
DD
= 5 V
= 5 V
SAMPLE
= 55 kHz, 600 Hz
REV. B