at40kal ATMEL Corporation, at40kal Datasheet - Page 12

• Manufacturer Part Number: at40kal
• Description: At40kal Military Reprogrammable Fpgas With Freeram
• Manufacturer: ATMEL Corporation

Figure 8. RAM Logic
12
WEN
Aout
Ain
Din
AT40KAL
5
5
4
“1”
0
1
data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or
WE is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled
together; they both select CLOCK (for a synchronous RAM) or they both select “1” (for
an asynchronous RAM). CLOCK is obtained from the clock for the sector-column imme-
diately to the left and immediately above the RAM block. Writing any value to the RAM
clear byte during configuration clears the RAM (see the “AT40KAL/KEL Configuration
Series” application note at www.atmel.com).
Figure 9 on page 13 shows an example of a RAM macro constructed using AT40KAL’s
FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note
the very small amount of external logic required to complete the address decoding for
the macro. Most of the logic cells (core cells) in the sectors occupied by the RAM will
be unused: they can be used for other logic in the design. This logic can be automati-
cally generated using the macro generators.
Latch
Latch
Latch
Load
Load
Load
CLOCK
Read Address
Write Address
Write Enable NOT
Din
RAM-Clear Byte
Dual-port
32 x 4
Clear
RAM
1
Load
“1”
0
Dout
“ 1 ”
OE
4
4263B–AERO–06/03
Dout