ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 118

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
Figure 2–74. Input Timing Diagram in DDR Mode
2–110
Arria GX Device Handbook, Volume 1
Input To
Logic Array
Data at
input pin
CLK
B0
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time.
Figure 2–76
A0
B1
A0
B0
A1
shows the DDR output timing diagram.
Figure 2–75
B2
A1
B1
A2
B3
A2
B2
shows the IOE configured for DDR output.
A3
B4
A3
B3
Altera Corporation
May 2008