ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 35

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode
Altera Corporation
May 2008
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
RX Phase
Compen-
Verify
BIST
BIST
sation
FIFO
Compensation
TX Phase
FIFO
Serializer
Byte
Reverse Serial Pre-CDR Loopback
Reverse serial pre-CDR loopback mode uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, loops back before the CRU
unit, and is transmitted though the high-speed differential transmitter
output buffer. It is for test or verification use only to verify the signal
being received after the gain and equalization improvements of the input
buffer. The signal at the output is not exactly what is received since the
signal goes through the output buffer and the V
setting level. Pre-emphasis settings have no effect.
20
serializer
Byte
De-
Encoder
8B/10B
Decoder
8B/10B
Generator
PRBS
BIST
Match
Rate
FIFO
Arria GX Device Handbook, Volume 1
Deskew
FIFO
PRBS
Verify
BIST
Aligner
Word
OD
is changed to the V
Analog Receiver and
Transmitter Logic
Arria GX Architecture
Serializer
serializer
De-
Reverse
Serial
Loopback
Recovery
Clock
Unit
2–27
OD