ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 81
ep1agx50d
Manufacturer Part Number
ep1agx50d
Description
Arria Gx Device Data Sheet
Manufacturer
Altera Corporation
Datasheet
1.EP1AGX50D.pdf
(296 pages)
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Altera Corporation
May 2008
Table 2–13
block multipliers can optionally feed an adder/subtractor or accumulator
in the block depending on the configuration, which makes routing to
ALMs easier, saves ALM routing resources, and increases performance
because all connections and blocks are in the DSP block.
Additionally, DSP block input registers can efficiently implement shift
registers for FIR filter applications. DSP blocks support Q1.15 format
rounding and saturation.
DSP block configured for 18 × 18-bit multiplier mode.
Note to
(1)
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
Table 2–13. DSP Blocks in Arria GX Devices
Device
This list only shows functions that can fit into a single DSP block. Multiple DSP
blocks can support larger multiplication functions.
Table
shows the number of DSP blocks in each Arria GX device. DSP
2–13:
DSP Blocks
10
14
26
32
44
Figure 2–51
Multipliers
Total 9 × 9
112
208
256
352
80
Arria GX Device Handbook, Volume 1
shows a top-level diagram of the
Note (1)
Total 18 × 18
Multipliers
104
128
176
40
56
Arria GX Architecture
Total 36 × 36
Multipliers
10
14
26
32
44
2–73
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