ep1agx50d Altera Corporation, ep1agx50d Datasheet - Page 128

• Manufacturer Part Number: ep1agx50d
• Description: Arria Gx Device Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
2–120
Arria GX Device Handbook, Volume 1
Note to
(1)
Series termination
Differential termination
Table 2–26. On-Chip Termination Support by I/O Banks
On-Chip Termination Support
Clock pins CLK1 and CLK3, and pins FPLL[7..8]CLK do not support differential on-chip termination. Clock pins
CLK0 and CLK2, do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7,
12..15]) do not support differential on-chip termination.
Table
2–26:
(1)
Table 2–26
bank.
Differential On-Chip Termination
Arria GX devices support internal differential termination with a nominal
resistance value of 100 Ω for LVDS input receiver buffers. LVPECL input
signals (supported on clock pins only) require an external termination
resistor. Differential on-chip termination is supported across the full
range of supported differential data rates as shown in the High-Speed I/O
Specifications section of the
volume 1 of the Arria GX Device Handbook.
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 class I and II
SSTL-18 class I
SSTL-18 class II
1.8-V HSTL class I
1.8-V HSTL class II
1.5-V HSTL class I
1.2-V HSTL
LVDS
HyperTransport technology
I/O Standard Support
shows the Arria GX on-chip termination support per I/O
DC & Switching Characteristics
Top and Bottom Banks
(3, 4, 7, 8)
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Altera Corporation
Left Bank (1, 2)
chapter in
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May 2008